sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

94

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1550

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1553

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2991

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2099

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6380

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7196

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6213

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5390

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4