sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

91

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1547

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1550

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2988

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2096

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6377

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7193

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6210

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5387

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0