sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

92

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1548

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1551

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2989

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2097

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6378

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7194

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6211

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5388

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1