sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

93

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1549

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1552

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2990

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2098

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6379

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7195

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6212

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5389

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2