sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

155

#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

109

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

155

#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

167

#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

169

#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

413

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

841

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1860

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1911

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3582

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2641

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

76

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

76

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

72

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

76

#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L