sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

251

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

38

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

251

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

273

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

275

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

456

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

949

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1968

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2017

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3688

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2747

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

125

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

125

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

121

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

125

#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L