sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

226

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

35

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

226

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

248

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

250

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

420

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

913

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1931

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1981

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3652

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2711

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

89

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

89

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

85

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6

sys/dev/pci/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

89

#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6