Symbol: SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
978
#define SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
1025
#define SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h
994
#define SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h
898
#define SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1