Symbol: SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
982
#define SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
1029
#define SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb
sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h
998
#define SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb