sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33525

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32546

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34368

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37611

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

29996

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20102

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23076

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24363

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24416

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26673

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7238

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7853

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8761

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9313

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000