sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33515

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32536

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34357

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37600

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

29985

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20091

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23066

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24353

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24406

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21856

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26663

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7228

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7839

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8741

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9293

#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1