sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

34760

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

34006

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

36083

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

39421

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

31550

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

21689

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23020

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24307

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24358

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21812

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26616

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7825

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8699

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9249

#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2