sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

34761

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

34007

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

36084

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

39422

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

31551

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

21690

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23021

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24308

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24359

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21813

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26617

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7827

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8701

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4

sys/dev/pci/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9251

#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4