/*      $NetBSD: platid_mask.c,v 1.25 2011/05/18 12:11:46 nonaka Exp $  */

/*-
 * Copyright (c) 1999-2001
 *         Shin Takemura and PocketBSD Project. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *        This product includes software developed by the NetBSD
 *        Foundation, Inc. and its contributors.
 * 4. Neither the name of The NetBSD Foundation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
/*
 *  Do not edit.
 *  This file is automatically generated by platid.awk.
 */
#include <machine/platid.h>
#include <machine/platid_mask.h>
#ifdef hpcmips
platid_t platid_mask_CPU_MIPS = {{
        PLATID_CPU_MIPS,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR = {{
        PLATID_CPU_MIPS_VR,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR_41XX = {{
        PLATID_CPU_MIPS_VR_41XX,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR_4102 = {{
        PLATID_CPU_MIPS_VR_4102,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR_4111 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR_4121 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR_4181 = {{
        PLATID_CPU_MIPS_VR_4181,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR_4122 = {{
        PLATID_CPU_MIPS_VR_4122,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR_4131 = {{
        PLATID_CPU_MIPS_VR_4131,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_VR_4181A = {{
        PLATID_CPU_MIPS_VR_4181A,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_TX = {{
        PLATID_CPU_MIPS_TX,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_TX_3900 = {{
        PLATID_CPU_MIPS_TX_3900,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_TX_3911 = {{
        PLATID_CPU_MIPS_TX_3911,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_TX_3912 = {{
        PLATID_CPU_MIPS_TX_3912,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_TX_3920 = {{
        PLATID_CPU_MIPS_TX_3920,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_TX_3922 = {{
        PLATID_CPU_MIPS_TX_3922,
        PLATID_WILD
}};
platid_t platid_mask_CPU_MIPS_TX_3927 = {{
        PLATID_CPU_MIPS_TX_3927,
        PLATID_WILD
}};
#endif /* hpcmips */
#ifdef hpcsh
platid_t platid_mask_CPU_SH = {{
        PLATID_CPU_SH,
        PLATID_WILD
}};
platid_t platid_mask_CPU_SH_3 = {{
        PLATID_CPU_SH_3,
        PLATID_WILD
}};
platid_t platid_mask_CPU_SH_3_7709 = {{
        PLATID_CPU_SH_3_7709,
        PLATID_WILD
}};
platid_t platid_mask_CPU_SH_3_7709A = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_WILD
}};
platid_t platid_mask_CPU_SH_3_7707 = {{
        PLATID_CPU_SH_3_7707,
        PLATID_WILD
}};
platid_t platid_mask_CPU_SH_4 = {{
        PLATID_CPU_SH_4,
        PLATID_WILD
}};
platid_t platid_mask_CPU_SH_4_7750 = {{
        PLATID_CPU_SH_4_7750,
        PLATID_WILD
}};
#endif /* hpcsh */
#ifdef hpcarm
platid_t platid_mask_CPU_ARM = {{
        PLATID_CPU_ARM,
        PLATID_WILD
}};
platid_t platid_mask_CPU_ARM_STRONGARM = {{
        PLATID_CPU_ARM_STRONGARM,
        PLATID_WILD
}};
platid_t platid_mask_CPU_ARM_STRONGARM_SA1100 = {{
        PLATID_CPU_ARM_STRONGARM_SA1100,
        PLATID_WILD
}};
platid_t platid_mask_CPU_ARM_STRONGARM_SA1110 = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_WILD
}};
platid_t platid_mask_CPU_ARM_XSCALE = {{
        PLATID_CPU_ARM_XSCALE,
        PLATID_WILD
}};
platid_t platid_mask_CPU_ARM_XSCALE_PXA250 = {{
        PLATID_CPU_ARM_XSCALE_PXA250,
        PLATID_WILD
}};
platid_t platid_mask_CPU_ARM_XSCALE_PXA270 = {{
        PLATID_CPU_ARM_XSCALE_PXA270,
        PLATID_WILD
}};
#endif /* hpcarm */
#ifdef hpcmips
platid_t platid_mask_MACH_NEC = {{
        PLATID_WILD,
        PLATID_MACH_NEC
}};
platid_t platid_mask_MACH_NEC_MCCS = {{
        PLATID_WILD,
        PLATID_MACH_NEC_MCCS
}};
platid_t platid_mask_MACH_NEC_MCCS_1X = {{
        PLATID_WILD,
        PLATID_MACH_NEC_MCCS_1X
}};
platid_t platid_mask_MACH_NEC_MCCS_11 = {{
        PLATID_CPU_MIPS_VR_4102,
        PLATID_MACH_NEC_MCCS_11
}};
platid_t platid_mask_MACH_NEC_MCCS_12 = {{
        PLATID_CPU_MIPS_VR_4102,
        PLATID_MACH_NEC_MCCS_12
}};
platid_t platid_mask_MACH_NEC_MCCS_13 = {{
        PLATID_CPU_MIPS_VR_4102,
        PLATID_MACH_NEC_MCCS_13
}};
platid_t platid_mask_MACH_NEC_MCR = {{
        PLATID_WILD,
        PLATID_MACH_NEC_MCR
}};
platid_t platid_mask_MACH_NEC_MCR_3XX = {{
        PLATID_CPU_MIPS_VR_41XX,
        PLATID_MACH_NEC_MCR_3XX
}};
platid_t platid_mask_MACH_NEC_MCR_300 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_NEC_MCR_300
}};
platid_t platid_mask_MACH_NEC_MCR_320 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_320
}};
platid_t platid_mask_MACH_NEC_MCR_FORDOCOMO = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_NEC_MCR_FORDOCOMO
}};
platid_t platid_mask_MACH_NEC_MCR_MPRO700 = {{
        PLATID_CPU_MIPS_VR_4102,
        PLATID_MACH_NEC_MCR_MPRO700
}};
platid_t platid_mask_MACH_NEC_MCR_330 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_330
}};
platid_t platid_mask_MACH_NEC_MCR_5XX = {{
        PLATID_CPU_MIPS_VR_41XX,
        PLATID_MACH_NEC_MCR_5XX
}};
platid_t platid_mask_MACH_NEC_MCR_500 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_NEC_MCR_500
}};
platid_t platid_mask_MACH_NEC_MCR_510 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_510
}};
platid_t platid_mask_MACH_NEC_MCR_520 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_520
}};
platid_t platid_mask_MACH_NEC_MCR_520A = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_520A
}};
platid_t platid_mask_MACH_NEC_MCR_500A = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_NEC_MCR_500A
}};
platid_t platid_mask_MACH_NEC_MCR_530 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_530
}};
platid_t platid_mask_MACH_NEC_MCR_430 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_430
}};
platid_t platid_mask_MACH_NEC_MCR_530A = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_530A
}};
platid_t platid_mask_MACH_NEC_MCR_SIGMARION = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_SIGMARION
}};
platid_t platid_mask_MACH_NEC_MCR_550 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_550
}};
platid_t platid_mask_MACH_NEC_MCR_450 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_450
}};
platid_t platid_mask_MACH_NEC_MCR_SIGMARION2 = {{
        PLATID_CPU_MIPS_VR_4131,
        PLATID_MACH_NEC_MCR_SIGMARION2
}};
platid_t platid_mask_MACH_NEC_MCR_7XX = {{
        PLATID_CPU_MIPS_VR_41XX,
        PLATID_MACH_NEC_MCR_7XX
}};
platid_t platid_mask_MACH_NEC_MCR_700 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_700
}};
platid_t platid_mask_MACH_NEC_MCR_700A = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_700A
}};
platid_t platid_mask_MACH_NEC_MCR_730 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_730
}};
platid_t platid_mask_MACH_NEC_MCR_730A = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_NEC_MCR_730A
}};
#endif /* hpcmips */
#ifdef hpcmips
platid_t platid_mask_MACH_EVEREX = {{
        PLATID_WILD,
        PLATID_MACH_EVEREX
}};
platid_t platid_mask_MACH_EVEREX_FREESTYLE = {{
        PLATID_WILD,
        PLATID_MACH_EVEREX_FREESTYLE
}};
platid_t platid_mask_MACH_EVEREX_FREESTYLE_AXX = {{
        PLATID_CPU_MIPS_VR_41XX,
        PLATID_MACH_EVEREX_FREESTYLE_AXX
}};
platid_t platid_mask_MACH_EVEREX_FREESTYLE_A10 = {{
        PLATID_CPU_MIPS_VR_4102,
        PLATID_MACH_EVEREX_FREESTYLE_A10
}};
platid_t platid_mask_MACH_EVEREX_FREESTYLE_A15 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_EVEREX_FREESTYLE_A15
}};
platid_t platid_mask_MACH_EVEREX_FREESTYLE_A20 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_EVEREX_FREESTYLE_A20
}};
#endif /* hpcmips */
platid_t platid_mask_MACH_CASIO = {{
        PLATID_WILD,
        PLATID_MACH_CASIO
}};
#ifdef hpcmips
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE = {{
        PLATID_WILD,
        PLATID_MACH_CASIO_CASSIOPEIAE
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_EXX = {{
        PLATID_WILD,
        PLATID_MACH_CASIO_CASSIOPEIAE_EXX
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E10 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_CASIO_CASSIOPEIAE_E10
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E11 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_CASIO_CASSIOPEIAE_E11
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E15 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_CASIO_CASSIOPEIAE_E15
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E55 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_CASIO_CASSIOPEIAE_E55
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_FORDOCOMO = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_CASIO_CASSIOPEIAE_FORDOCOMO
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E65 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_CASIO_CASSIOPEIAE_E65
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_EXXX = {{
        PLATID_WILD,
        PLATID_MACH_CASIO_CASSIOPEIAE_EXXX
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E100 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_CASIO_CASSIOPEIAE_E100
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E105 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_CASIO_CASSIOPEIAE_E105
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E500 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_CASIO_CASSIOPEIAE_E500
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAE_E507 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_CASIO_CASSIOPEIAE_E507
}};
platid_t platid_mask_MACH_CASIO_POCKETPOSTPET = {{
        PLATID_WILD,
        PLATID_MACH_CASIO_POCKETPOSTPET
}};
platid_t platid_mask_MACH_CASIO_POCKETPOSTPET_POCKETPOSTPET = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_CASIO_POCKETPOSTPET_POCKETPOSTPET
}};
#endif /* hpcmips */
#ifdef hpcsh
platid_t platid_mask_MACH_CASIO_CASSIOPEIAA = {{
        PLATID_WILD,
        PLATID_MACH_CASIO_CASSIOPEIAA
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAA_AXX = {{
        PLATID_WILD,
        PLATID_MACH_CASIO_CASSIOPEIAA_AXX
}};
platid_t platid_mask_MACH_CASIO_CASSIOPEIAA_A55V = {{
        PLATID_CPU_SH_3_7709,
        PLATID_MACH_CASIO_CASSIOPEIAA_A55V
}};
#endif /* hpcsh */
#if defined(hpcmips) || defined(hpcarm)
platid_t platid_mask_MACH_SHARP = {{
        PLATID_WILD,
        PLATID_MACH_SHARP
}};
#if defined(hpcmips)
platid_t platid_mask_MACH_SHARP_TRIPAD = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_TRIPAD
}};
platid_t platid_mask_MACH_SHARP_TRIPAD_PV = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_TRIPAD_PV
}};
platid_t platid_mask_MACH_SHARP_TRIPAD_PV6000 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_SHARP_TRIPAD_PV6000
}};
platid_t platid_mask_MACH_SHARP_TELIOS = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_TELIOS
}};
platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_TELIOS_HCAJ
}};
platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ1_JP = {{
        PLATID_CPU_MIPS_TX_3922,
        PLATID_MACH_SHARP_TELIOS_HCAJ1_JP
}};
platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ2_JP = {{
        PLATID_CPU_MIPS_TX_3922,
        PLATID_MACH_SHARP_TELIOS_HCAJ2_JP
}};
platid_t platid_mask_MACH_SHARP_TELIOS_HCAJ3_JP = {{
        PLATID_CPU_MIPS_TX_3922,
        PLATID_MACH_SHARP_TELIOS_HCAJ3_JP
}};
platid_t platid_mask_MACH_SHARP_TELIOS_HCVJ = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_TELIOS_HCVJ
}};
platid_t platid_mask_MACH_SHARP_TELIOS_HCVJ1C_JP = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_TELIOS_HCVJ1C_JP
}};
platid_t platid_mask_MACH_SHARP_MOBILON = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_MOBILON
}};
platid_t platid_mask_MACH_SHARP_MOBILON_HC = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_MOBILON_HC
}};
platid_t platid_mask_MACH_SHARP_MOBILON_HC4100 = {{
        PLATID_CPU_MIPS_TX_3912,
        PLATID_MACH_SHARP_MOBILON_HC4100
}};
platid_t platid_mask_MACH_SHARP_MOBILON_HC4500 = {{
        PLATID_CPU_MIPS_TX_3912,
        PLATID_MACH_SHARP_MOBILON_HC4500
}};
platid_t platid_mask_MACH_SHARP_MOBILON_HC1200 = {{
        PLATID_CPU_MIPS_TX_3912,
        PLATID_MACH_SHARP_MOBILON_HC1200
}};
#endif /* hpcmips */
#if defined(hpcarm)
platid_t platid_mask_MACH_SHARP_WZERO3 = {{
        PLATID_WILD,
        PLATID_MACH_SHARP_WZERO3
}};
platid_t platid_mask_MACH_SHARP_WZERO3_WS003SH = {{
        PLATID_CPU_ARM_XSCALE_PXA270,
        PLATID_MACH_SHARP_WZERO3_WS003SH
}};
platid_t platid_mask_MACH_SHARP_WZERO3_WS004SH = {{
        PLATID_CPU_ARM_XSCALE_PXA270,
        PLATID_MACH_SHARP_WZERO3_WS004SH
}};
platid_t platid_mask_MACH_SHARP_WZERO3_WS007SH = {{
        PLATID_CPU_ARM_XSCALE_PXA270,
        PLATID_MACH_SHARP_WZERO3_WS007SH
}};
platid_t platid_mask_MACH_SHARP_WZERO3_WS011SH = {{
        PLATID_CPU_ARM_XSCALE_PXA270,
        PLATID_MACH_SHARP_WZERO3_WS011SH
}};
platid_t platid_mask_MACH_SHARP_WZERO3_WS020SH = {{
        PLATID_CPU_ARM_XSCALE_PXA270,
        PLATID_MACH_SHARP_WZERO3_WS020SH
}};
#endif /* hpcarm */
#endif /* hpcmips || hpcarm */
#ifdef hpcmips
platid_t platid_mask_MACH_FUJITSU = {{
        PLATID_WILD,
        PLATID_MACH_FUJITSU
}};
platid_t platid_mask_MACH_FUJITSU_INTERTOP = {{
        PLATID_WILD,
        PLATID_MACH_FUJITSU_INTERTOP
}};
platid_t platid_mask_MACH_FUJITSU_INTERTOP_ITXXX = {{
        PLATID_WILD,
        PLATID_MACH_FUJITSU_INTERTOP_ITXXX
}};
platid_t platid_mask_MACH_FUJITSU_INTERTOP_IT300 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_FUJITSU_INTERTOP_IT300
}};
platid_t platid_mask_MACH_FUJITSU_INTERTOP_IT310 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_FUJITSU_INTERTOP_IT310
}};
platid_t platid_mask_MACH_FUJITSU_PENCENTRA = {{
        PLATID_WILD,
        PLATID_MACH_FUJITSU_PENCENTRA
}};
platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_FUJITSU_PENCENTRA_130
}};
platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130TM = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_FUJITSU_PENCENTRA_130TM
}};
platid_t platid_mask_MACH_FUJITSU_PENCENTRA_130RF = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_FUJITSU_PENCENTRA_130RF
}};
platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200 = {{
        PLATID_CPU_MIPS_TX_3922,
        PLATID_MACH_FUJITSU_PENCENTRA_200
}};
platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200CTM = {{
        PLATID_CPU_MIPS_TX_3922,
        PLATID_MACH_FUJITSU_PENCENTRA_200CTM
}};
platid_t platid_mask_MACH_FUJITSU_PENCENTRA_200CRF = {{
        PLATID_CPU_MIPS_TX_3922,
        PLATID_MACH_FUJITSU_PENCENTRA_200CRF
}};
#endif /* hpcmips */
#ifdef hpcmips
platid_t platid_mask_MACH_PHILIPS = {{
        PLATID_WILD,
        PLATID_MACH_PHILIPS
}};
platid_t platid_mask_MACH_PHILIPS_NINO = {{
        PLATID_WILD,
        PLATID_MACH_PHILIPS_NINO
}};
platid_t platid_mask_MACH_PHILIPS_NINO_3XX = {{
        PLATID_WILD,
        PLATID_MACH_PHILIPS_NINO_3XX
}};
platid_t platid_mask_MACH_PHILIPS_NINO_312 = {{
        PLATID_CPU_MIPS_TX_3912,
        PLATID_MACH_PHILIPS_NINO_312
}};
#endif /* hpcmips */
platid_t platid_mask_MACH_COMPAQ = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ
}};
#ifdef hpcmips
platid_t platid_mask_MACH_COMPAQ_C = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_C
}};
platid_t platid_mask_MACH_COMPAQ_C_8XX = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_C_8XX
}};
platid_t platid_mask_MACH_COMPAQ_C_810 = {{
        PLATID_CPU_MIPS_TX_3912,
        PLATID_MACH_COMPAQ_C_810
}};
platid_t platid_mask_MACH_COMPAQ_C_201X = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_C_201X
}};
platid_t platid_mask_MACH_COMPAQ_C_2010 = {{
        PLATID_CPU_MIPS_TX_3912,
        PLATID_MACH_COMPAQ_C_2010
}};
platid_t platid_mask_MACH_COMPAQ_C_2015 = {{
        PLATID_CPU_MIPS_TX_3912,
        PLATID_MACH_COMPAQ_C_2015
}};
platid_t platid_mask_MACH_COMPAQ_AERO = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_AERO
}};
platid_t platid_mask_MACH_COMPAQ_AERO_15XX = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_AERO_15XX
}};
platid_t platid_mask_MACH_COMPAQ_AERO_1530 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_COMPAQ_AERO_1530
}};
platid_t platid_mask_MACH_COMPAQ_AERO_21XX = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_AERO_21XX
}};
platid_t platid_mask_MACH_COMPAQ_AERO_2110 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_COMPAQ_AERO_2110
}};
platid_t platid_mask_MACH_COMPAQ_AERO_2130 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_COMPAQ_AERO_2130
}};
platid_t platid_mask_MACH_COMPAQ_AERO_2140 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_COMPAQ_AERO_2140
}};
platid_t platid_mask_MACH_COMPAQ_PRESARIO = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_PRESARIO
}};
platid_t platid_mask_MACH_COMPAQ_PRESARIO_21X = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_PRESARIO_21X
}};
platid_t platid_mask_MACH_COMPAQ_PRESARIO_213 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_COMPAQ_PRESARIO_213
}};
#endif /* hpcmips */
#ifdef hpcarm
platid_t platid_mask_MACH_COMPAQ_IPAQ = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_IPAQ
}};
platid_t platid_mask_MACH_COMPAQ_IPAQ_H31XX = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_IPAQ_H31XX
}};
platid_t platid_mask_MACH_COMPAQ_IPAQ_H3100 = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_COMPAQ_IPAQ_H3100
}};
platid_t platid_mask_MACH_COMPAQ_IPAQ_H36XX = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_IPAQ_H36XX
}};
platid_t platid_mask_MACH_COMPAQ_IPAQ_H3600 = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_COMPAQ_IPAQ_H3600
}};
platid_t platid_mask_MACH_COMPAQ_IPAQ_H3660 = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_COMPAQ_IPAQ_H3660
}};
platid_t platid_mask_MACH_COMPAQ_IPAQ_H39XX = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_IPAQ_H39XX
}};
platid_t platid_mask_MACH_COMPAQ_IPAQ_H3900 = {{
        PLATID_CPU_ARM_XSCALE_PXA250,
        PLATID_MACH_COMPAQ_IPAQ_H3900
}};
#endif /* hpcarm */
#ifdef hpcsh
platid_t platid_mask_MACH_COMPAQ_AERO = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_AERO
}};
platid_t platid_mask_MACH_COMPAQ_AERO_8000 = {{
        PLATID_WILD,
        PLATID_MACH_COMPAQ_AERO_8000
}};
#endif /* hpcsh */
#ifdef hpcmips
platid_t platid_mask_MACH_VICTOR = {{
        PLATID_WILD,
        PLATID_MACH_VICTOR
}};
platid_t platid_mask_MACH_VICTOR_INTERLINK = {{
        PLATID_WILD,
        PLATID_MACH_VICTOR_INTERLINK
}};
platid_t platid_mask_MACH_VICTOR_INTERLINK_MP = {{
        PLATID_WILD,
        PLATID_MACH_VICTOR_INTERLINK_MP
}};
platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC101 = {{
        PLATID_CPU_MIPS_TX_3922,
        PLATID_MACH_VICTOR_INTERLINK_MPC101
}};
platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC303 = {{
        PLATID_CPU_MIPS_VR_4122,
        PLATID_MACH_VICTOR_INTERLINK_MPC303
}};
platid_t platid_mask_MACH_VICTOR_INTERLINK_MPC304 = {{
        PLATID_CPU_MIPS_VR_4122,
        PLATID_MACH_VICTOR_INTERLINK_MPC304
}};
#endif /* hpcmips */
#ifdef hpcmips
platid_t platid_mask_MACH_IBM = {{
        PLATID_WILD,
        PLATID_MACH_IBM
}};
platid_t platid_mask_MACH_IBM_WORKPAD = {{
        PLATID_WILD,
        PLATID_MACH_IBM_WORKPAD
}};
platid_t platid_mask_MACH_IBM_WORKPAD_Z50 = {{
        PLATID_WILD,
        PLATID_MACH_IBM_WORKPAD_Z50
}};
platid_t platid_mask_MACH_IBM_WORKPAD_26011AU = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_IBM_WORKPAD_26011AU
}};
#endif /* hpcmips */
#ifdef hpcmips
platid_t platid_mask_MACH_VADEM = {{
        PLATID_WILD,
        PLATID_MACH_VADEM
}};
platid_t platid_mask_MACH_VADEM_CLIO = {{
        PLATID_WILD,
        PLATID_MACH_VADEM_CLIO
}};
platid_t platid_mask_MACH_VADEM_CLIO_C = {{
        PLATID_WILD,
        PLATID_MACH_VADEM_CLIO_C
}};
platid_t platid_mask_MACH_VADEM_CLIO_C1000 = {{
        PLATID_CPU_MIPS_VR_4111,
        PLATID_MACH_VADEM_CLIO_C1000
}};
platid_t platid_mask_MACH_VADEM_CLIO_C1050 = {{
        PLATID_CPU_MIPS_VR_4121,
        PLATID_MACH_VADEM_CLIO_C1050
}};
#endif /* hpcmips */
platid_t platid_mask_MACH_HP = {{
        PLATID_WILD,
        PLATID_MACH_HP
}};
#ifdef hpcsh
platid_t platid_mask_MACH_HP_LX = {{
        PLATID_WILD,
        PLATID_MACH_HP_LX
}};
platid_t platid_mask_MACH_HP_LX_620 = {{
        PLATID_CPU_SH_3_7709,
        PLATID_MACH_HP_LX_620
}};
platid_t platid_mask_MACH_HP_LX_620JP = {{
        PLATID_CPU_SH_3_7709,
        PLATID_MACH_HP_LX_620JP
}};
platid_t platid_mask_MACH_HP_LX_360 = {{
        PLATID_CPU_SH_3_7707,
        PLATID_MACH_HP_LX_360
}};
#endif /* hpcsh */
platid_t platid_mask_MACH_HP_JORNADA = {{
        PLATID_WILD,
        PLATID_MACH_HP_JORNADA
}};
#ifdef hpcsh
platid_t platid_mask_MACH_HP_JORNADA_6XX = {{
        PLATID_WILD,
        PLATID_MACH_HP_JORNADA_6XX
}};
platid_t platid_mask_MACH_HP_JORNADA_680 = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_680
}};
platid_t platid_mask_MACH_HP_JORNADA_680JP = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_680JP
}};
platid_t platid_mask_MACH_HP_JORNADA_680EU = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_680EU
}};
platid_t platid_mask_MACH_HP_JORNADA_680DE = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_680DE
}};
platid_t platid_mask_MACH_HP_JORNADA_690 = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_690
}};
platid_t platid_mask_MACH_HP_JORNADA_690JP = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_690JP
}};
platid_t platid_mask_MACH_HP_JORNADA_690EU = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_690EU
}};
platid_t platid_mask_MACH_HP_JORNADA_690DE = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_690DE
}};
platid_t platid_mask_MACH_HP_JORNADA_680FR = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_680FR
}};
platid_t platid_mask_MACH_HP_JORNADA_690FR = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_690FR
}};
platid_t platid_mask_MACH_HP_JORNADA_680SV = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_680SV
}};
platid_t platid_mask_MACH_HP_JORNADA_690SV = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_690SV
}};
platid_t platid_mask_MACH_HP_JORNADA_680ES = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_680ES
}};
platid_t platid_mask_MACH_HP_JORNADA_690ES = {{
        PLATID_CPU_SH_3_7709A,
        PLATID_MACH_HP_JORNADA_690ES
}};
#endif /* hpcsh */
#ifdef hpcarm
platid_t platid_mask_MACH_HP_JORNADA_7XX = {{
        PLATID_WILD,
        PLATID_MACH_HP_JORNADA_7XX
}};
platid_t platid_mask_MACH_HP_JORNADA_720 = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_HP_JORNADA_720
}};
platid_t platid_mask_MACH_HP_JORNADA_720JP = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_HP_JORNADA_720JP
}};
platid_t platid_mask_MACH_HP_JORNADA_720EU = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_HP_JORNADA_720EU
}};
platid_t platid_mask_MACH_HP_JORNADA_720DE = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_HP_JORNADA_720DE
}};
platid_t platid_mask_MACH_HP_JORNADA_720FR = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_HP_JORNADA_720FR
}};
platid_t platid_mask_MACH_HP_JORNADA_720SV = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_HP_JORNADA_720SV
}};
platid_t platid_mask_MACH_HP_JORNADA_720ES = {{
        PLATID_CPU_ARM_STRONGARM_SA1110,
        PLATID_MACH_HP_JORNADA_720ES
}};
platid_t platid_mask_MACH_HP_JORNADA_8XX = {{
        PLATID_WILD,
        PLATID_MACH_HP_JORNADA_8XX
}};
platid_t platid_mask_MACH_HP_JORNADA_820 = {{
        PLATID_CPU_ARM_STRONGARM_SA1100,
        PLATID_MACH_HP_JORNADA_820
}};
platid_t platid_mask_MACH_HP_JORNADA_820JP = {{
        PLATID_CPU_ARM_STRONGARM_SA1100,
        PLATID_MACH_HP_JORNADA_820JP
}};
#endif /* hpcarm */
#ifdef hpcsh
platid_t platid_mask_MACH_HITACHI = {{
        PLATID_WILD,
        PLATID_MACH_HITACHI
}};
platid_t platid_mask_MACH_HITACHI_PERSONA = {{
        PLATID_WILD,
        PLATID_MACH_HITACHI_PERSONA
}};
platid_t platid_mask_MACH_HITACHI_PERSONA_HPW230JC = {{
        PLATID_CPU_SH_3_7709,
        PLATID_MACH_HITACHI_PERSONA_HPW230JC
}};
platid_t platid_mask_MACH_HITACHI_PERSONA_HPW50PAD = {{
        PLATID_CPU_SH_3_7709,
        PLATID_MACH_HITACHI_PERSONA_HPW50PAD
}};
platid_t platid_mask_MACH_HITACHI_PERSONA_HPW200EC = {{
        PLATID_CPU_SH_3_7709,
        PLATID_MACH_HITACHI_PERSONA_HPW200EC
}};
platid_t platid_mask_MACH_HITACHI_PERSONA_HPW650PA = {{
        PLATID_CPU_SH_4_7750,
        PLATID_MACH_HITACHI_PERSONA_HPW650PA
}};
#endif /* hpcsh */
#ifdef hpcsh
platid_t platid_mask_MACH_LGE = {{
        PLATID_WILD,
        PLATID_MACH_LGE
}};
platid_t platid_mask_MACH_LGE_PHENOM = {{
        PLATID_WILD,
        PLATID_MACH_LGE_PHENOM
}};
platid_t platid_mask_MACH_LGE_PHENOM_H220C = {{
        PLATID_CPU_SH_3_7709,
        PLATID_MACH_LGE_PHENOM_H220C
}};
#endif /* hpcsh */
#ifdef hpcmips
platid_t platid_mask_MACH_LASER5 = {{
        PLATID_WILD,
        PLATID_MACH_LASER5
}};
platid_t platid_mask_MACH_LASER5_L = {{
        PLATID_WILD,
        PLATID_MACH_LASER5_L
}};
platid_t platid_mask_MACH_LASER5_L_CARD = {{
        PLATID_CPU_MIPS_VR_4181,
        PLATID_MACH_LASER5_L_CARD
}};
platid_t platid_mask_MACH_LASER5_L_BOARD = {{
        PLATID_CPU_MIPS_VR_4122,
        PLATID_MACH_LASER5_L_BOARD
}};
#endif /* hpcmips */
#ifdef hpcmips
platid_t platid_mask_MACH_AGENDA = {{
        PLATID_WILD,
        PLATID_MACH_AGENDA
}};
platid_t platid_mask_MACH_AGENDA_VR = {{
        PLATID_WILD,
        PLATID_MACH_AGENDA_VR
}};
platid_t platid_mask_MACH_AGENDA_VR_VR3 = {{
        PLATID_CPU_MIPS_VR_4181,
        PLATID_MACH_AGENDA_VR_VR3
}};
#endif /* hpcmips */
#ifdef hpcarm
platid_t platid_mask_MACH_PSIONTEKLOGIX = {{
        PLATID_WILD,
        PLATID_MACH_PSIONTEKLOGIX
}};
platid_t platid_mask_MACH_PSIONTEKLOGIX_NETBOOK = {{
        PLATID_WILD,
        PLATID_MACH_PSIONTEKLOGIX_NETBOOK
}};
platid_t platid_mask_MACH_PSIONTEKLOGIX_NETBOOK_PRO = {{
        PLATID_CPU_ARM_XSCALE_PXA250,
        PLATID_MACH_PSIONTEKLOGIX_NETBOOK_PRO
}};
#endif /* hpcarm */