#include <machine/asm.h>
#include "assym.h"
__RCSID("$NetBSD: spl.S,v 1.8 2023/06/12 19:04:14 skrll Exp $")
#define SZINT (1 << INT_SCALESHIFT)
.data
.globl _C_LABEL(ipl_sie_map)
.type _C_LABEL(ipl_sie_map), @object
.p2align INT_SCALESHIFT
_C_LABEL(ipl_sie_map):
.word 0
.word 0
.word 0
.word 0
.word 0
.word SIE_SEIE
.word SIE_SEIE | SIE_STIE
.word SIE_SEIE | SIE_STIE | SIE_SSIE
ENTRY_NP(splx)
PTR_L a3, L_CPU(tp)
INT_L t0, CI_CPL(a3)
bge a0, t0, 2f
sll t2, a0, INT_SCALESHIFT
PTR_LA a1, _C_LABEL(ipl_sie_map)
add a1, a1, t2
INT_L a1, 0(a1)
li t2, (SIE_SEIE | SIE_STIE | SIE_SSIE)
xor a1, a1, t2
INT_S a0, CI_CPL(a3)
csrs sie, a1
#ifdef __HAVE_FAST_SOFTINTS
INT_L t4, CI_SOFTINTS(a3)
srl t4, t4, a0
beqz t4, 3f
tail _C_LABEL(softint_deliver)
3:
#endif
2:
ret
END(splx)
#if IPL_NONE != 0
#error IPL_NONE is not 0
#endif
ENTRY_NP(spl0)
PTR_L a3, L_CPU(tp)
INT_S zero, CI_CPL(a3)
li t2, (SIE_SEIE | SIE_STIE | SIE_SSIE)
csrs sie, t2
csrsi sstatus, SR_SIE
#ifdef __HAVE_FAST_SOFTINTS
tail _C_LABEL(softint_deliver)
#else
ret
#endif
END(spl0)
ENTRY(splintr)
csrr t0, sip
li t1, IPL_NONE
andi t0, t0, (SIP_SEIP | SIP_STIP | SIP_SSIP)
beq t0, zero, 1f
PTR_LA t3, _C_LABEL(ipl_sie_map)
li t1, IPL_VM
li t2, IPL_HIGH + 1
2:
INT_L t5, IPL_VM * (1 << INT_SCALESHIFT)(t3)
PTR_ADDI t3, t3, 1 << INT_SCALESHIFT
not t5, t5
and t5, t5, t0
beq t5, zero, 1f
addi t1, t1, 1
bne t1, t2, 2b
1:
LONG_S t0, 0(a0)
mv a0, t1
jr ra
END(splintr)
ENTRY_NP(splsoftclock)
li t1, IPL_SOFTCLOCK
INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTCLOCK
j _splraise
END(splsoftclock)
ENTRY_NP(splsoftbio)
li t1, IPL_SOFTBIO
INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTBIO
j _splraise
END(splsoftbio)
ENTRY_NP(splsoftnet)
li t1, IPL_SOFTNET
INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTNET
j _splraise
END(splsoftnet)
ENTRY_NP(splsoftserial)
li t1, IPL_SOFTSERIAL
INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SOFTSERIAL
j _splraise
END(splsoftserial)
ENTRY_NP(splvm)
li t1, IPL_VM
INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_VM
j _splraise
END(splvm)
ENTRY_NP(splsched)
li t1, IPL_SCHED
INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_SCHED
j _splraise
END(splsched)
ENTRY_NP(splhigh)
li t1, IPL_HIGH
INT_L t0, _C_LABEL(ipl_sie_map) + SZINT * IPL_HIGH
j _splraise
END(splhigh)
ENTRY_NP(splraise)
mv t1, a0
sll t2, a0, INT_SCALESHIFT
PTR_LA a1, _C_LABEL(ipl_sie_map)
add a1, a1, t2
INT_L t0, 0(a1)
_splraise:
PTR_L a3, L_CPU(tp)
INT_L a0, CI_CPL(a3)
bge a0, t1, 2f
csrc sie, t0
INT_S t1, CI_CPL(a3)
2:
ret
END(splraise)