sys/arch/hpcmips/dev/mq200.c

186

mq200_win_enable(sc, MQ200_GC2, mode,

sys/arch/hpcmips/dev/mq200debug.c

153

reg = mq200_read(sc, MQ200_GCCR(MQ200_GC2));

sys/arch/hpcmips/dev/mq200machdep.c

195

sc->sc_width[MQ200_GC2] = mdp->md_fp_width;

sys/arch/hpcmips/dev/mq200machdep.c

196

sc->sc_height[MQ200_GC2] = mdp->md_fp_height;

sys/arch/hpcmips/dev/mq200subr.c

202

[MQ200_I_GCC(MQ200_GC2)] = MQ200_GCCR(MQ200_GC2),

sys/arch/hpcmips/dev/mq200subr.c

230

mq200_write2(sc, &sc->sc_regctxs[MQ200_I_GCC(MQ200_GC2)], 0);

sys/arch/hpcmips/dev/mq200subr.c

311

mq200_write2(sc, &sc->sc_regctxs[MQ200_I_GCC(MQ200_GC2)],

sys/arch/hpcmips/dev/mq200subr.c

313

(clock->gc[MQ200_GC2] << MQ200_GCC_RCLK_SHIFT) |

sys/arch/hpcmips/dev/mq200subr.c

316

mq200_clknames[clock->gc[MQ200_GC2]]);