sys/arch/hpcmips/dev/mq200.c

191

mq200_win_enable(sc, MQ200_GC1, mode,

sys/arch/hpcmips/dev/mq200debug.c

131

reg = mq200_read(sc, MQ200_GCCR(MQ200_GC1));

sys/arch/hpcmips/dev/mq200subr.c

201

[MQ200_I_GCC(MQ200_GC1)] = MQ200_GCCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

227

mq200_write2(sc, &sc->sc_regctxs[MQ200_I_GCC(MQ200_GC1)], 0);

sys/arch/hpcmips/dev/mq200subr.c

243

mq200_set_pll(sc, clock->gc[MQ200_GC1], crt->clock);

sys/arch/hpcmips/dev/mq200subr.c

265

mq200_write(sc, MQ200_GCHDCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

270

mq200_write(sc, MQ200_GCVDCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

275

mq200_write(sc, MQ200_GCHSCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

280

mq200_write(sc, MQ200_GCVSCR(MQ200_GC1),

sys/arch/hpcmips/dev/mq200subr.c

286

mq200_write2(sc, &sc->sc_regctxs[MQ200_I_GCC(MQ200_GC1)],

sys/arch/hpcmips/dev/mq200subr.c

288

(clock->gc[MQ200_GC1] << MQ200_GCC_RCLK_SHIFT) |

sys/arch/hpcmips/dev/mq200subr.c

296

sc->sc_width[MQ200_GC1] = crt->width;

sys/arch/hpcmips/dev/mq200subr.c

297

sc->sc_height[MQ200_GC1] = crt->height;

sys/arch/hpcmips/dev/mq200subr.c

300

mq200_clknames[clock->gc[MQ200_GC1]]);