sys/arch/hpcmips/dev/mq200reg.h

101

#define MQ200_GCCR(n) (MQ200_GC(n)+0x00)

sys/arch/hpcmips/dev/mq200reg.h

199

#define MQ200_GCHDCR(n) (MQ200_GC(n)+0x08)

sys/arch/hpcmips/dev/mq200reg.h

208

#define MQ200_GCVDCR(n) (MQ200_GC(n)+0x0c)

sys/arch/hpcmips/dev/mq200reg.h

217

#define MQ200_GCHSCR(n) (MQ200_GC(n)+0x10)

sys/arch/hpcmips/dev/mq200reg.h

226

#define MQ200_GCVSCR(n) (MQ200_GC(n)+0x14)

sys/arch/hpcmips/dev/mq200reg.h

240

#define MQ200_GCWHCR(n) (MQ200_GC(n)+0x20)

sys/arch/hpcmips/dev/mq200reg.h

251

#define MQ200_GCWVCR(n) (MQ200_GC(n)+0x24)

sys/arch/hpcmips/dev/mq200reg.h

260

#define MQ200_GCAWHCR(n) (MQ200_GC(n)+0x28)

sys/arch/hpcmips/dev/mq200reg.h

271

#define MQ200_GCAWVCR(n) (MQ200_GC(n)+0x2C)

sys/arch/hpcmips/dev/mq200reg.h

280

#define MQ200_GCWSAR(n) (MQ200_GC(n)+0x30)

sys/arch/hpcmips/dev/mq200reg.h

285

#define MQ200_GCAWSAR(n) (MQ200_GC(n)+0x34)

sys/arch/hpcmips/dev/mq200reg.h

293

#define MQ200_GCWSTR(n) (MQ200_GC(n)+0x38)

sys/arch/hpcmips/dev/mq200reg.h

308

#define MQ200_GCHCPR(n) (MQ200_GC(n)+0x40)

sys/arch/hpcmips/dev/mq200reg.h

317

#define MQ200_GCHCAOR(n) (MQ200_GC(n)+0x44)

sys/arch/hpcmips/dev/mq200reg.h

329

#define MQ200_GCHCFCR(n) (MQ200_GC(n)+0x48)

sys/arch/hpcmips/dev/mq200reg.h

335

#define MQ200_GCHCBCR(n) (MQ200_GC(n)+0x4c)

sys/arch/hpcmips/dev/mq200reg.h

99

#define MQ200_GCR(n) (MQ200_GC(0)+(n)*4)