sys/arch/evbmips/ingenic/clock.c

120

printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));

sys/arch/evbmips/ingenic/clock.c

126

printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));

sys/arch/evbmips/ingenic/clock.c

131

printf("SR: %08x\n", MFC0(MIPS_COP_0_STATUS, 0));

sys/arch/mips/mips/db_disasm.c

639

if (i.RType.rd == MIPS_COP_0_STATUS

sys/arch/mips/mips/db_interface.c

477

SHOW32(MIPS_COP_0_STATUS, "status");

sys/arch/mips/mips/mips_dsp.c

131

[cp0_status] "n"(MIPS_COP_0_STATUS));

sys/arch/mips/mips/mips_dsp.c

189

[cp0_status] "n"(MIPS_COP_0_STATUS));

sys/arch/mips/mips/mips_fpu.c

116

"n"(MIPS_COP_0_STATUS));

sys/arch/mips/mips/mips_fpu.c

206

__asm volatile ("mtc0 %0, $%1" :: "r"(status), "n"(MIPS_COP_0_STATUS));

sys/arch/mips/mips/mips_fpu.c

246

: "r"(tf->tf_regs[_R_SR] & (MIPS_SR_COP_1_BIT|MIPS3_SR_FR|MIPS_SR_KX|MIPS_SR_INT_IE)), "n"(MIPS_COP_0_STATUS));

sys/arch/mips/mips/mips_fpu.c

352

"n"(MIPS_COP_0_STATUS));

sys/arch/mips/rmi/rmixl_fmnvar.h

205

: "n"(MIPS_COP_0_STATUS), "n"(1 << 30));

sys/arch/mips/rmi/rmixl_fmnvar.h

226

: "n"(MIPS_COP_0_STATUS), "r"(mask), "r"(ocu));