MHz
case 0x00000000: mvTclk = 166 MHz; break;
case 0x00800000: mvTclk = 125 MHz; break;
case 0x000000a0: mvPclk = 1000 MHz; break;
case 0x000000c0: mvPclk = 933 MHz; break;
case 0x000000e0: mvPclk = 933 MHz; break;
case 0x00000100: mvPclk = 800 MHz; break;
case 0x00000120: mvPclk = 800 MHz; break;
case 0x00000140: mvPclk = 800 MHz; break;
case 0x00000160: mvPclk = 1067 MHz; break;
case 0x00000180: mvPclk = 667 MHz; break;
case 0x000001a0: mvPclk = 533 MHz; break;
case 0x000001c0: mvPclk = 400 MHz; break;
case 0x000001e0: mvPclk = 333 MHz; break;
mvTclk = 200 MHz;
case 0x00000014: mvPclk = 600 MHz; break;
case 0x00000018: mvPclk = 800 MHz; break;
mvSysclk = 200 MHz;
case 0x00000002: mvPclk = 400 MHz; break;
case 0x00000008: mvPclk = 600 MHz; break;
case 0x00400008: mvPclk = 800 MHz; break;
case 0x0040000a: mvPclk = 1000 MHz; break;
case 0x00000012: mvPclk = 1200 MHz; break;
case 0x00000018: mvPclk = 1500 MHz; break;
case 0x0000001a: mvPclk = 1600 MHz; break;
case 0x00400018: mvPclk = 1800 MHz; break;
case 0x0040001a: mvPclk = 2000 MHz; break;
case 0x080: mvTclk = 200 MHz; break;
default: mvTclk = 200 MHz; break;
case 0x020: mvSysclk = 200 MHz; break;
case 0x080: mvSysclk = 400 MHz; break;
case 0x0a0: mvSysclk = 250 MHz; break;
case 0x0c0: mvSysclk = 300 MHz; break;
(processor_frequency + 4999) / MHz,
((processor_frequency + 4999) / (MHz/100)) % 100);
#define GHz (1000L * MHz)
#define ID16(MHz, mV, bus_clk) \
((((MHz * 100 + 50) / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
135 MHz },
110 MHz },
175 MHz },
75 MHz },
74 MHz },
69 MHz },
65 MHz },
50 MHz },
40 MHz },