Symbol: MESON_CLK_PLL_REG
sys/arch/arm/amlogic/meson8b_clkc.c
185
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
sys/arch/arm/amlogic/meson8b_clkc.c
186
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
sys/arch/arm/amlogic/meson8b_clkc.c
187
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
sys/arch/arm/amlogic/meson8b_clkc.c
189
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
sys/arch/arm/amlogic/meson8b_clkc.c
190
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
sys/arch/arm/amlogic/meson8b_clkc.c
240
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
sys/arch/arm/amlogic/meson8b_clkc.c
241
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
sys/arch/arm/amlogic/meson8b_clkc.c
242
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
sys/arch/arm/amlogic/meson8b_clkc.c
243
MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
sys/arch/arm/amlogic/meson8b_clkc.c
244
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
sys/arch/arm/amlogic/meson8b_clkc.c
245
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
sys/arch/arm/amlogic/meson8b_clkc.c
259
MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
sys/arch/arm/amlogic/meson8b_clkc.c
260
MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/meson8b_clkc.c
261
MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
sys/arch/arm/amlogic/meson8b_clkc.c
262
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
sys/arch/arm/amlogic/meson8b_clkc.c
265
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
sys/arch/arm/amlogic/meson8b_clkc.c
266
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/meson8b_clkc.c
267
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
sys/arch/arm/amlogic/meson8b_clkc.c
271
MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BITS(13,0)), /* sdm */
sys/arch/arm/amlogic/meson8b_clkc.c
272
MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/meson8b_clkc.c
273
MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BITS(24,16)), /* n2 */
sys/arch/arm/amlogic/meson_clk.h
239
#define MESON_CLK_PLL_REG_INVALID MESON_CLK_PLL_REG(0,0)
sys/arch/arm/amlogic/mesong12_clkc.c
187
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
188
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(7,0)), /* m */ \
sys/arch/arm/amlogic/mesong12_clkc.c
189
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(14,10)),/* n */ \
sys/arch/arm/amlogic/mesong12_clkc.c
190
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL1, __BITS(16,0)), /* frac */ \
sys/arch/arm/amlogic/mesong12_clkc.c
191
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(31)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
192
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
205
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
206
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(7,0)), /* m */ \
sys/arch/arm/amlogic/mesong12_clkc.c
207
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(14,10)),/* n */ \
sys/arch/arm/amlogic/mesong12_clkc.c
209
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(31)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
210
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
223
MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
224
MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BITS(7,0)), /* m */ \
sys/arch/arm/amlogic/mesong12_clkc.c
225
MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BITS(14,10)),/* n */ \
sys/arch/arm/amlogic/mesong12_clkc.c
227
MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(31)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
228
MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
305
MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BITS(13,0)), /* sdm */ \
sys/arch/arm/amlogic/mesong12_clkc.c
306
MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BIT(30)), /* sdm_enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
307
MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BITS(28,20)), /* n2 */ \
sys/arch/arm/amlogic/mesong12_clkc.c
308
MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BIT(29)), /* ssen */ \
sys/arch/arm/amlogic/mesong12_clkc.c
313
MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BITS(13,0)), /* sdm */ \
sys/arch/arm/amlogic/mesong12_clkc.c
314
MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BIT(30)), /* sdm_enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
315
MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BITS(28,20)), /* n2 */ \
sys/arch/arm/amlogic/mesong12_clkc.c
316
MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BIT(29)), /* ssen */ \
sys/arch/arm/amlogic/mesong12_clkc.c
321
MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BITS(13,0)), /* sdm */ \
sys/arch/arm/amlogic/mesong12_clkc.c
322
MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BIT(30)), /* sdm_enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
323
MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BITS(28,20)), /* n2 */ \
sys/arch/arm/amlogic/mesong12_clkc.c
324
MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BIT(29)), /* ssen */ \
sys/arch/arm/amlogic/mesong12_clkc.c
903
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
904
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BITS(7,0)), /* m */ \
sys/arch/arm/amlogic/mesong12_clkc.c
905
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BITS(14,10)),/* n */ \
sys/arch/arm/amlogic/mesong12_clkc.c
906
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL1, __BITS(15,0)),/* frac */ \
sys/arch/arm/amlogic/mesong12_clkc.c
907
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(30)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
908
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
951
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
952
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BITS(7,0)), /* m */ \
sys/arch/arm/amlogic/mesong12_clkc.c
953
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BITS(14,10)),/* n */ \
sys/arch/arm/amlogic/mesong12_clkc.c
954
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL1, __BITS(11,0)),/* frac */ \
sys/arch/arm/amlogic/mesong12_clkc.c
955
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(31)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
956
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesongxbb_clkc.c
100
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
sys/arch/arm/amlogic/mesongxbb_clkc.c
101
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
sys/arch/arm/amlogic/mesongxbb_clkc.c
110
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
111
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
sys/arch/arm/amlogic/mesongxbb_clkc.c
112
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
sys/arch/arm/amlogic/mesongxbb_clkc.c
113
MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
sys/arch/arm/amlogic/mesongxbb_clkc.c
114
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
sys/arch/arm/amlogic/mesongxbb_clkc.c
115
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
sys/arch/arm/amlogic/mesongxbb_clkc.c
129
MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
sys/arch/arm/amlogic/mesongxbb_clkc.c
130
MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
131
MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
sys/arch/arm/amlogic/mesongxbb_clkc.c
132
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
sys/arch/arm/amlogic/mesongxbb_clkc.c
135
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
sys/arch/arm/amlogic/mesongxbb_clkc.c
136
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
137
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
sys/arch/arm/amlogic/mesongxbb_clkc.c
141
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
sys/arch/arm/amlogic/mesongxbb_clkc.c
142
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
143
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
sys/arch/arm/amlogic/mesongxbb_clkc.c
96
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
97
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
sys/arch/arm/amlogic/mesongxbb_clkc.c
98
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */