MESON_CLK_GATE
MESON_CLK_GATE(MESON8B_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
MESON_CLK_GATE(MESON8B_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14),
MESON_CLK_GATE(MESON8B_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14),
MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27),
MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28),
MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29),
MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30),
MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31),
MESON_CLK_GATE(MESON8B_CLOCK_CLK81, "clk81", "mpeg_div", HHI_MPEG_CLK_CNTL, 7),
MESON_CLK_GATE(MESON8B_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
MESON_CLK_GATE(MESON8B_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
MESON_CLK_GATE(MESON8B_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12),
MESON_CLK_GATE(MESON8B_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13),
MESON_CLK_GATE(MESON8B_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14),
MESON_CLK_GATE(MESON8B_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17),
MESON_CLK_GATE(MESON8B_CLOCK_ETH, "eth", "clk81", HHI_GCLK_MPEG1, 3),
MESON_CLK_GATE(MESON8B_CLOCK_UART1, "uart1", "clk81", HHI_GCLK_MPEG1, 16),
MESON_CLK_GATE(MESON8B_CLOCK_USB0, "usb0", "clk81", HHI_GCLK_MPEG1, 21),
MESON_CLK_GATE(MESON8B_CLOCK_USB1, "usb1", "clk81", HHI_GCLK_MPEG1, 22),
MESON_CLK_GATE(MESON8B_CLOCK_USB, "usb", "clk81", HHI_GCLK_MPEG1, 26),
MESON_CLK_GATE(MESON8B_CLOCK_EFUSE, "efuse", "clk81", HHI_GCLK_MPEG1, 30),
MESON_CLK_GATE(MESON8B_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 8),
MESON_CLK_GATE(MESON8B_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9),
MESON_CLK_GATE(MESON8B_CLOCK_UART2, "uart2", "clk81", HHI_GCLK_MPEG2, 15),
case MESON_CLK_GATE: type = "gate"; break;
.type = MESON_CLK_GATE, \
KASSERT(clk->type == MESON_CLK_GATE);
KASSERT(clk->type == MESON_CLK_GATE);
MESON_CLK_GATE(MESONG12_CLOCK_AO_AHB, "ahb_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_IR_IN,"ir_in_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_I2C_M0, "i2c_m0_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_I2C_S0, "i2c_s0_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_UART, "uart_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_PROD_I2C, "prod_i2c_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_UART2, "uart2_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_IR_OUT, "ir_out_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_SAR_ADC, "sar_adc_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_MAILBOX, "mailbox_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_M3, "m3_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_AHB_SRAM, "ahb_sram_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_RTI, "rti_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_M4_FCLK, "m4_fclk_ao",
MESON_CLK_GATE(MESONG12_CLOCK_AO_M4_HCLK, "m4_hclk_ao",
MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV2, "fclk_div2", \
MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV3, "fclk_div3", \
MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV4, "fclk_div4", \
MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV5, "fclk_div5", \
MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV7, "fclk_div7", \
MESON_CLK_GATE(MESONG12_CLOCK_MPLL0, "mpll0", \
MESON_CLK_GATE(MESONG12_CLOCK_MPLL1, "mpll1", \
MESON_CLK_GATE(MESONG12_CLOCK_MPLL2, "mpll2", \
MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_A_CLK0, "sd_emmc_a_clk0", \
MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_B_CLK0, "sd_emmc_b_clk0", \
MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_C_CLK0, "sd_emmc_c_clk0", \
MESON_CLK_GATE(MESONG12_CLOCK_CLK81, "clk81", \
MESON_CLK_GATE(MESONG12_CLOCK_DDR, "ddr", \
MESON_CLK_GATE(MESONG12_CLOCK_DOS, "dos", \
MESON_CLK_GATE(MESONG12_CLOCK_AUDIO_LOCKER, "audio_locker", \
MESON_CLK_GATE(MESONG12_CLOCK_MIPI_DSI_HOST, "mipi_dsi_host", \
MESON_CLK_GATE(MESONG12_CLOCK_ETH_PHY, "eth_phy", \
MESON_CLK_GATE(MESONG12_CLOCK_ISA, "isa", \
MESON_CLK_GATE(MESONG12_CLOCK_PL301, "pl301", \
MESON_CLK_GATE(MESONG12_CLOCK_PERIPHS, "periphs", \
MESON_CLK_GATE(MESONG12_CLOCK_SPICC0, "spicc0", \
MESON_CLK_GATE(MESONG12_CLOCK_I2C, "i2c", \
MESON_CLK_GATE(MESONG12_CLOCK_SANA, "sana", \
MESON_CLK_GATE(MESONG12_CLOCK_SD, "sd", \
MESON_CLK_GATE(MESONG12_CLOCK_RNG0, "rng0", \
MESON_CLK_GATE(MESONG12_CLOCK_UART0, "uart0", \
MESON_CLK_GATE(MESONG12_CLOCK_SPICC1, "spicc1", \
MESON_CLK_GATE(MESONG12_CLOCK_HIU_IFACE, "hiu_iface", \
MESON_CLK_GATE(MESONG12_CLOCK_MIPI_DSI_PHY, "mipi_dsi_phy", \
MESON_CLK_GATE(MESONG12_CLOCK_ASSIST_MISC, "assist_misc", \
MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_A, "sd_emmc_a", \
MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_B, "sd_emmc_b", \
MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_C, "sd_emmc_c", \
MESON_CLK_GATE(MESONG12_CLOCK_AUDIO_CODEC, "audio_codec", \
MESON_CLK_GATE(MESONG12_CLOCK_AUDIO, "audio", \
MESON_CLK_GATE(MESONG12_CLOCK_ETH, "eth", \
MESON_CLK_GATE(MESONG12_CLOCK_DEMUX, "demux", \
MESON_CLK_GATE(MESONG12_CLOCK_AUDIO_IFIFO, "audio_ififo", \
MESON_CLK_GATE(MESONG12_CLOCK_ADC, "adc", \
MESON_CLK_GATE(MESONG12_CLOCK_UART1, "uart1", \
MESON_CLK_GATE(MESONG12_CLOCK_G2D, "g2d", \
MESON_CLK_GATE(MESONG12_CLOCK_RESET, "reset", \
MESON_CLK_GATE(MESONG12_CLOCK_PCIE_COMB, "pcie_comb", \
MESON_CLK_GATE(MESONG12_CLOCK_PARSER, "parser", \
MESON_CLK_GATE(MESONG12_CLOCK_USB, "usb", \
MESON_CLK_GATE(MESONG12_CLOCK_PCIE_PHY, "pcie_phy", \
MESON_CLK_GATE(MESONG12_CLOCK_AHB_ARB0, "ahb_arb0", \
MESON_CLK_GATE(MESONG12_CLOCK_AHB_DATA_BUS, "ahb_data_bus", \
MESON_CLK_GATE(MESONG12_CLOCK_AHB_CTRL_BUS, "ahb_ctrl_bus", \
MESON_CLK_GATE(MESONG12_CLOCK_HTX_HDCP22, "htx_hdcp22", \
MESON_CLK_GATE(MESONG12_CLOCK_HTX_PCLK, "htx_pclk", \
MESON_CLK_GATE(MESONG12_CLOCK_BT656, "bt656", \
MESON_CLK_GATE(MESONG12_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", \
MESON_CLK_GATE(MESONG12_CLOCK_MMC_PCLK, "mmc_pclk", \
MESON_CLK_GATE(MESONG12_CLOCK_UART2, "uart2", \
MESON_CLK_GATE(MESONG12_CLOCK_VPU_INTR, "vpu_intr", \
MESON_CLK_GATE(MESONG12_CLOCK_GIC, "gic", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCI0, "vclk2_venci0", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCI1, "vclk2_venci1", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCP0, "vclk2_vencp0", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCP1, "vclk2_vencp1", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCT0, "vclk2_venct0", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCT1, "vclk2_venct1", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_OTHER, "vclk2_other", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_ENCI, "vclk2_enci", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_ENCP, "vclk2_encp", \
MESON_CLK_GATE(MESONG12_CLOCK_DAC_CLK, "dac_clk", \
MESON_CLK_GATE(MESONG12_CLOCK_AOCLK, "aoclk", \
MESON_CLK_GATE(MESONG12_CLOCK_IEC958, "iec958", \
MESON_CLK_GATE(MESONG12_CLOCK_ENC480P, "enc480p", \
MESON_CLK_GATE(MESONG12_CLOCK_RNG1, "rng1", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_ENCT, "vclk2_enct", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_ENCL, "vclk2_encl", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCLMMC, "vclk2_venclmmc", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCL, "vclk2_vencl", \
MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_OTHER1, "vclk2_other1", \
MESON_CLK_GATE(MESONG12_CLOCK_DMA, "dma", \
MESON_CLK_GATE(MESONG12_CLOCK_EFUSE, "efuse", \
MESON_CLK_GATE(MESONG12_CLOCK_ROM_BOOT, "rom_boot", \
MESON_CLK_GATE(MESONG12_CLOCK_RESET_SEC, "reset_sec", \
MESON_CLK_GATE(MESONG12_CLOCK_SEC_AHB_APB3, "sec_ahb_apb3", \
MESON_CLK_GATE(MESONG12_CLOCK_TS, "ts", \
MESON_CLK_GATE(MESONG12_CLOCK_VID_PLL, "vid_pll", \
MESON_CLK_GATE(MESONGXBB_CLOCK_AO_REMOTE, "remote_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 0),
MESON_CLK_GATE(MESONGXBB_CLOCK_AO_I2C_MASTER, "i2c_master_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 1),
MESON_CLK_GATE(MESONGXBB_CLOCK_AO_I2C_SLAVE, "i2c_slave_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 2),
MESON_CLK_GATE(MESONGXBB_CLOCK_AO_UART1, "uart1_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 3),
MESON_CLK_GATE(MESONGXBB_CLOCK_AO_UART2, "uart2_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 5),
MESON_CLK_GATE(MESONGXBB_CLOCK_AO_IR_BLASTER, "ir_blaster_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 6),
MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14),
MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14),
MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27),
MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28),
MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29),
MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30),
MESON_CLK_GATE(MESONGXBB_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_A_CLK0, "sd_emmc_a_clk0", "sd_emmc_a_clk0_div", HHI_SD_EMMC_CLK_CNTL, 7),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_B_CLK0, "sd_emmc_b_clk0", "sd_emmc_b_clk0_div", HHI_SD_EMMC_CLK_CNTL, 23),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_C_CLK0, "sd_emmc_c_clk0", "sd_emmc_c_clk0_div", HHI_NAND_CLK_CNTL, 7),
MESON_CLK_GATE(MESONGXBB_CLOCK_CLK81, "clk81", "mpeg_div", HHI_MPEG_CLK_CNTL, 7),
MESON_CLK_GATE(MESONGXBB_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
MESON_CLK_GATE(MESONGXBB_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
MESON_CLK_GATE(MESONGXBB_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12),
MESON_CLK_GATE(MESONGXBB_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13),
MESON_CLK_GATE(MESONGXBB_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14),
MESON_CLK_GATE(MESONGXBB_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_A, "sd_emmc_a", "clk81", HHI_GCLK_MPEG0, 24),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_B, "sd_emmc_b", "clk81", HHI_GCLK_MPEG0, 25),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_C, "sd_emmc_c", "clk81", HHI_GCLK_MPEG0, 26),
MESON_CLK_GATE(MESONGXBB_CLOCK_ETH, "eth", "clk81", HHI_GCLK_MPEG1, 3),
MESON_CLK_GATE(MESONGXBB_CLOCK_UART1, "uart1", "clk81", HHI_GCLK_MPEG1, 16),
MESON_CLK_GATE(MESONGXBB_CLOCK_USB0, "usb0", "clk81", HHI_GCLK_MPEG1, 21),
MESON_CLK_GATE(MESONGXBB_CLOCK_USB1, "usb1", "clk81", HHI_GCLK_MPEG1, 22),
MESON_CLK_GATE(MESONGXBB_CLOCK_USB, "usb", "clk81", HHI_GCLK_MPEG1, 26),
MESON_CLK_GATE(MESONGXBB_CLOCK_EFUSE, "efuse", "clk81", HHI_GCLK_MPEG1, 30),
MESON_CLK_GATE(MESONGXBB_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 8),
MESON_CLK_GATE(MESONGXBB_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9),
MESON_CLK_GATE(MESONGXBB_CLOCK_UART2, "uart2", "clk81", HHI_GCLK_MPEG2, 15),