MESON_CLK_FIXED_FACTOR
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV2, "cpu_in_div2", "cpu_in_sel", 2, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV3, "cpu_in_div3", "cpu_in_sel", 3, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV2, "cpu_clk_div2", "cpu_clk", 2, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV3, "cpu_clk_div3", "cpu_clk", 3, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV4, "cpu_clk_div4", "cpu_clk", 4, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV5, "cpu_clk_div5", "cpu_clk", 5, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV6, "cpu_clk_div6", "cpu_clk", 6, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV7, "cpu_clk_div7", "cpu_clk", 7, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV8, "cpu_clk_div8", "cpu_clk", 8, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", "pll_fixed", 2, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV3_DIV, "fclk_div3_div", "pll_fixed", 3, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", "pll_fixed", 4, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", "pll_fixed", 5, 1),
MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", "pll_fixed", 7, 1),
case MESON_CLK_FIXED_FACTOR: type = "fixed-factor"; break;
.type = MESON_CLK_FIXED_FACTOR, \
KASSERT(clk->type == MESON_CLK_FIXED_FACTOR);
KASSERT(clk->type == MESON_CLK_FIXED_FACTOR);
KASSERT(clk->type == MESON_CLK_FIXED_FACTOR);
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV2P5_DIV, \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV3_DIV, \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_MPLL_PREDIV, "mpll_prediv", \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_MPLL_50M_DIV, "mpll_50m_div", \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_PCIE_PLL_DCO_DIV2, \
MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_PCIE_PLL, "pcie_pll_pll", \
MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", "pll_fixed", 2, 1),
MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV3_DIV, "fclk_div3_div", "pll_fixed", 3, 1),
MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", "pll_fixed", 4, 1),
MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", "pll_fixed", 5, 1),
MESON_CLK_FIXED_FACTOR(MESONGXBB_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", "pll_fixed", 7, 1),