LCG_REG
LCG_REG(LCG_REG_GRAPHICS_CONTROL) = 0xd8000000; /* gfx reset, FIFO and AG enable */
LCG_REG(LCG_REG_WRITE_PROTECT_LOW_HIGH) = 0xffff0000;
LCG_REG(LCG_REG_FIFO_BASE) = sc->sc_dm->dm_segs[0].ds_addr;
LCG_REG(LCG_REG_FIFO_BASE2) = sc->sc_dm->dm_segs[0].ds_addr;
LCG_REG(LCG_REG_FIFO_MASKS) = 0xffff;
LCG_REG(LCG_REG_FIFO_SAVE_HEAD_OFFSET) = sc->sc_dm->dm_segs[0].ds_addr;
LCG_REG(LCG_REG_GRAPHICS_INT_STATUS) = 0xffffffff;
LCG_REG(LCG_REG_GRAPHICS_INT_SET_ENABLE) = 0;
LCG_REG(LCG_REG_GRAPHICS_INT_CLR_ENABLE) = 0xffffffff;
LCG_REG(LCG_REG_LCG_GO) = 3; /* FIFO and AG go */
LCG_REG(LCG_REG_VIDEO_CONFIG) = video_conf;
LCG_REG(LCG_REG_LUT_CONSOLE_SEL) = 1;
LCG_REG(LCG_REG_LUT_COLOR_BASE_W) = LCG_LUT_OFFSET;
LCG_REG(LCG_REG_LUT_CONSOLE_SEL) = 0;
status = LCG_REG(LCG_REG_GRAPHICS_SUB_STATUS);
status = LCG_REG(LCG_REG_GRAPHICS_SUB_STATUS);