ARM_PFR1_SEC_MASK
(armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 ||
|| (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0;
&& (armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0) {
(armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 ||
(armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 ||
(armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 ||
(armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 ||
(armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 ||
KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0);
(armreg_pfr1_read() & ARM_PFR1_SEC_MASK) == 0 ||
KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0);