LCA_MEMC_BASE
#define LCA_MEMC_BCR0 (LCA_MEMC_BASE + 0x00) /* Bank Configuration 0 */
#define LCA_MEMC_BCR1 (LCA_MEMC_BASE + 0x08) /* Bank Configuration 1 */
#define LCA_MEMC_BCR2 (LCA_MEMC_BASE + 0x10) /* Bank Configuration 2 */
#define LCA_MEMC_BCR3 (LCA_MEMC_BASE + 0x18) /* Bank Configuration 3 */
#define LCA_MEMC_BMR0 (LCA_MEMC_BASE + 0x20) /* Bank Address Mask 0 */
#define LCA_MEMC_BMR1 (LCA_MEMC_BASE + 0x28) /* Bank Address Mask 1 */
#define LCA_MEMC_BMR2 (LCA_MEMC_BASE + 0x30) /* Bank Address Mask 2 */
#define LCA_MEMC_BMR3 (LCA_MEMC_BASE + 0x38) /* Bank Address Mask 3 */
#define LCA_MEMC_BTR0 (LCA_MEMC_BASE + 0x40) /* Bank Timing 0 */
#define LCA_MEMC_BTR1 (LCA_MEMC_BASE + 0x48) /* Bank Timing 1 */
#define LCA_MEMC_BTR2 (LCA_MEMC_BASE + 0x50) /* Bank Timing 2 */
#define LCA_MEMC_BTR3 (LCA_MEMC_BASE + 0x58) /* Bank Timing 3 */
#define LCA_MEMC_GTR (LCA_MEMC_BASE + 0x60) /* Global Timing */
#define LCA_MEMC_ESR (LCA_MEMC_BASE + 0x68) /* Error Status */
#define LCA_MEMC_EAR (LCA_MEMC_BASE + 0x70) /* Error Address */
#define LCA_MEMC_CAR (LCA_MEMC_BASE + 0x78) /* Cache */
#define LCA_MEMC_VGR (LCA_MEMC_BASE + 0x80) /* Video and Graphics Control */
#define LCA_MEMC_PLM (LCA_MEMC_BASE + 0x88) /* Plane mask */
#define LCA_MEMC_FOR (LCA_MEMC_BASE + 0x90) /* Foreground */