L3CR_L3RT
{ L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" },
{ L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" },
{ L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" },