sys/arch/arm/arm32/pmap.c

7260

pte_l1_s_cache_mode = L1_S_B|L1_S_C;

sys/arch/arm/arm32/pmap.c

7288

pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;

sys/arch/arm/arm32/pmap.c

7292

pte_l1_s_cache_mode_pt = L1_S_C; /* write through */

sys/arch/arm/arm32/pmap.c

7349

pte_l1_s_cache_mode = L1_S_C;

sys/arch/arm/arm32/pmap.c

7357

pte_l1_s_cache_mode_pt = L1_S_C;

sys/arch/arm/arm32/pmap.c

7375

pte_l1_s_cache_mode = L1_S_B | L1_S_C;

sys/arch/arm/arm32/pmap.c

7383

pte_l1_s_cache_mode_pt = L1_S_C;

sys/arch/arm/arm32/pmap.c

7401

pte_l1_s_cache_mode = L1_S_C;

sys/arch/arm/arm32/pmap.c

7409

pte_l1_s_cache_mode_pt = L1_S_C;

sys/arch/arm/arm32/pmap.c

7428

pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;

sys/arch/arm/arm32/pmap.c

7447

pte_l1_s_cache_mode = L1_S_B|L1_S_C;

sys/arch/arm/arm32/pmap.c

7459

pte_l1_s_cache_mode_pt = L1_S_C;

sys/arch/arm/arm32/pmap.c

7513

pte_l1_s_cache_mode = L1_S_C;

sys/arch/arm/arm32/pmap.c

7666

pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01);

sys/arch/arm/arm32/pmap.c

7677

pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01);

sys/arch/arm/include/arm32/pmap.h

849

#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)

sys/arch/arm/include/arm32/pmap.h

850

#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X))

sys/arch/arm/include/arm32/pmap.h

851

#define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX))

sys/arch/arm/include/arm32/pmap.h

852

#define L1_S_CACHE_MASK_armv6n (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)

sys/arch/arm/include/arm32/pmap.h

853

#define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)