Symbol: JZ_TC_TESR
sys/arch/evbmips/ingenic/clock.c
106
writereg(JZ_TC_TESR, TESR_TCST5); /* enable timer 5 */
sys/arch/evbmips/ingenic/machdep.c
122
writereg(JZ_TC_TESR, TESR_OST);