sys/arch/riscv/starfive/jh7110_pinctrl.c

110

#define JH7110_PADCFG_DS_2MA __SHIFTIN(0, JH7110_PADCFG_DS_MASK)

sys/arch/riscv/starfive/jh7110_pinctrl.c

111

#define JH7110_PADCFG_DS_4MA __SHIFTIN(1, JH7110_PADCFG_DS_MASK)

sys/arch/riscv/starfive/jh7110_pinctrl.c

112

#define JH7110_PADCFG_DS_8MA __SHIFTIN(2, JH7110_PADCFG_DS_MASK)

sys/arch/riscv/starfive/jh7110_pinctrl.c

113

#define JH7110_PADCFG_DS_12MA __SHIFTIN(3, JH7110_PADCFG_DS_MASK)

sys/arch/riscv/starfive/jh7110_pinctrl.c

470

*mask |= JH7110_PADCFG_DS_MASK;

sys/arch/riscv/starfive/jh7110_pinctrl.c

474

*mask |= JH7110_PADCFG_DS_MASK;

sys/arch/riscv/starfive/jh7110_pinctrl.c

478

*mask |= JH7110_PADCFG_DS_MASK;

sys/arch/riscv/starfive/jh7110_pinctrl.c

482

*mask |= JH7110_PADCFG_DS_MASK;