IXL_DMA_LEN
0, IXL_DMA_LEN(&sc->sc_atq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_atq),
memset(IXL_DMA_KVA(&sc->sc_arq), 0, IXL_DMA_LEN(&sc->sc_arq));
memset(IXL_DMA_KVA(&sc->sc_atq), 0, IXL_DMA_LEN(&sc->sc_atq));
0, IXL_DMA_LEN(&rxr->rxr_mem),
0, IXL_DMA_LEN(&rxr->rxr_mem),
memset(IXL_DMA_KVA(&rxr->rxr_mem), 0, IXL_DMA_LEN(&rxr->rxr_mem));
0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD);
0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD);
0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE);
0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE);
memset(IXL_DMA_KVA(&txr->txr_mem), 0, IXL_DMA_LEN(&txr->txr_mem));
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE);
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE);
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD);
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD);
0, IXL_DMA_LEN(&sc->sc_atq),
0, IXL_DMA_LEN(&sc->sc_atq),
0, IXL_DMA_LEN(&sc->sc_atq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_atq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_atq),
0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_PREWRITE);
0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE);
0, IXL_DMA_LEN(&sc->sc_hmc_pd), BUS_DMASYNC_POSTWRITE);
0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE);
0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE);
0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD);
0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD);
0, IXL_DMA_LEN(&rxr->rxr_mem),
0, IXL_DMA_LEN(&rxr->rxr_mem),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_arq),
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE);
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE);
0, IXL_DMA_LEN(&sc->sc_atq),
0, IXL_DMA_LEN(&sc->sc_atq),
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE);
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE);
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD);
0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD);
IXL_DMA_LEN(&idm), BUS_DMASYNC_PREREAD);
IXL_DMA_LEN(&idm), BUS_DMASYNC_POSTREAD);
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm),
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm),
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm),
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm),
(IXL_DMA_LEN(idm) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0));
iaq.iaq_datalen = htole16(IXL_DMA_LEN(idm));
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm),
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm),
(IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0));
iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi));
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi),
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi),
(IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0));
iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi));
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi),
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi),
memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm));
IXL_DMA_LEN(idm), BUS_DMASYNC_PREWRITE);
IXL_DMA_LEN(idm), BUS_DMASYNC_POSTWRITE);
dmalen = MIN(lutlen, IXL_DMA_LEN(idm));
memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm));
IXL_DMA_LEN(idm), BUS_DMASYNC_PREWRITE);
IXL_DMA_LEN(idm), BUS_DMASYNC_POSTWRITE);
memset(kva, 0, IXL_DMA_LEN(&sc->sc_hmc_pd));
0, IXL_DMA_LEN(&sc->sc_hmc_pd),
memset(sdpage, 0, IXL_DMA_LEN(&sc->sc_hmc_sd));
0, IXL_DMA_LEN(&sc->sc_hmc_sd),
if (len > IXL_DMA_LEN(idm))
memset(IXL_DMA_KVA(idm), 0, IXL_DMA_LEN(idm));
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm),
bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm),