ISP_READ
l = ISP_READ(isp, SXP_PINS_DIFF) & ISP1080_MODE_MASK;
l = ISP_READ(isp, SXP_PINS_DIFF|SXP_BANK1_SELECT);
i = ISP_READ(isp, BIU_CONF0) & BIU_CONF0_HW_MASK;
if (ISP_READ(isp, SXP_PINS_DIFF) & SXP_PINS_DIFF_MODE) {
i = ISP_READ(isp, RISC_PSR);
isp->isp_mboxtmp[i] = ISP_READ(isp, MBOX_OFF(i));
ISP_WRITE(isp, isp->isp_respoutrp, ISP_READ(isp, isp->isp_respinrp));
iptr = ISP_READ(isp, BIU2400_ATIO_RSPINP);
optr = ISP_READ(isp, BIU2400_ATIO_RSPOUTP);
val = ISP_READ(isp, BIU2400_CSR);
optr = ISP_READ(isp, isp->isp_respoutrp);
iptr = ISP_READ(isp, isp->isp_respinrp);
junk = ISP_READ(isp, isp->isp_respinrp);
iptr = ISP_READ(isp, isp->isp_respinrp);
iptr = ISP_READ(isp, isp->isp_respinrp);
junk = ISP_READ(isp, BIU_R2HSTSLO);
junk = ISP_READ(isp, BIU_ISR);
sema = ISP_READ(isp, BIU_SEMA);
mbox = ISP_READ(isp, OUTMAILBOX0);
val = ISP_READ(isp, OUTMAILBOX0);
val = ISP_READ(isp, BIU2400_CSR);
isp->isp_reqodx = ISP_READ(isp, isp->isp_rqstoutrp);
chan = ISP_READ(isp, OUTMAILBOX6);
if (!(ISP_READ(isp, BIU_ICR) & BIU_ICR_SOFT_RESET)) {
mbox = ISP_READ(isp, isp->isp_rqstoutrp);
if (ISP_READ(isp, OUTMAILBOX0) == 0) {
mbox = ISP_READ(isp, OUTMAILBOX2);
if (!(ISP_READ(isp, BIU2100_CSR) & BIU2100_SOFT_RESET))
h1 = (ISP_READ(isp, OUTMAILBOX2) << 16) | ISP_READ(isp, OUTMAILBOX1);
h1 = (ISP_READ(isp, OUTMAILBOX2) << 16) | ISP_READ(isp, OUTMAILBOX1);
h2 = (ISP_READ(isp, OUTMAILBOX7) << 16) | ISP_READ(isp, OUTMAILBOX6);
chan = ISP_READ(isp, OUTMAILBOX3) & 0xff; \
chan = ISP_READ(isp, OUTMAILBOX6);
isp_fastpost_complete(isp, (ISP_READ(isp, OUTMAILBOX2) << 16) | ISP_READ(isp, OUTMAILBOX1));
if (isp_target_async(isp, (ISP_READ(isp, OUTMAILBOX2) << 16) | ISP_READ(isp, OUTMAILBOX1), mbox)) {
nphdl = ISP_READ(isp, OUTMAILBOX1);
nlstate = ISP_READ(isp, OUTMAILBOX2);
reason = ISP_READ(isp, OUTMAILBOX3) >> 8;
mbox = ISP_READ(isp, OUTMAILBOX1);
val = ISP_READ(isp, OUTMAILBOX0);
while (ISP_READ(isp, RISC_MTR) != 0x1313) {
while (ISP_READ(isp, OUTMAILBOX0) == MBOX_BUSY) {
(void)ISP_READ(isp, BIU_NVRAM); /* force PCI flush */
(void)ISP_READ(isp, BIU_NVRAM); /* force PCI flush */
(void)ISP_READ(isp, BIU_NVRAM); /* force PCI flush */
rv = ISP_READ(isp, BIU_NVRAM);
(void)ISP_READ(isp, BIU_NVRAM); /* force PCI flush */
(void)ISP_READ(isp, BIU_NVRAM); /* force PCI flush */
tmp = ISP_READ(isp, BIU2400_FLASH_ADDR);
*rp = ISP_READ(isp, BIU2400_FLASH_DATA);
isp->isp_reqodx = ISP_READ(isp, isp->isp_rqstoutrp);
mbox1 = ISP_READ(isp, OUTMAILBOX1);
bus = ISP_READ(isp, OUTMAILBOX6);
(ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \
(IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \
(ISP_READ(isp, BIU_ICR) & BIU2100_IMASK)))
(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) | (val))
(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) & ~(val))
printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
ISP_READ(isp, CDMA_FIFO_STS));
ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
ISP_READ(isp, DDMA_FIFO_STS));
ISP_READ(isp, SXP_INTERRUPT),
ISP_READ(isp, SXP_GROSS_ERR),
ISP_READ(isp, SXP_PINS_CTRL));
ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
ISP_READ(isp, OUTMAILBOX4));