IPUV3_WRITE
IPUV3_WRITE(sc, cm, IPU_CM_CONF, reg);
IPUV3_WRITE(sc, dmfc, IPU_DMFC_IC_CTRL,
IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN, 0x00000000);
IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN_DEF, 0x20202020);
IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN, 0x00000094);
IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN_DEF, 0x202020F6);
IPUV3_WRITE(sc, dmfc, IPU_DMFC_GENERAL1,
IPUV3_WRITE(sc, dc, addr, reg);
IPUV3_WRITE(sc, dc, addr, reg);
IPUV3_WRITE(sc, dc, addr, reg);
IPUV3_WRITE(sc, dctmpl, index * 8, reg);
IPUV3_WRITE(sc, dctmpl, index * 8 + 4, reg);
IPUV3_WRITE(sc, dc, IPU_DC_RL(base, evt), reg);
IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_5, reg);
IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_1, 0x4);
IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_ADDR_5, 0x0);
IPUV3_WRITE(sc, dc, IPU_DC_GEN, 0x44);
IPUV3_WRITE(sc, dc, IPU_DC_DISP_CONF2_0, width);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(no), reg_gen0);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(no), reg_gen1);
IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(no), reg);
IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN0, div);
IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN1,
IPUV3_WRITE(sc, di0, IPU_DI_DW_GEN(0), reg);
IPUV3_WRITE(sc, di0, IPU_DI_DW_SET(0, 3), reg);
IPUV3_WRITE(sc, di0, IPU_DI_SCR_CONF,
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(6), 0);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(6), 0);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(7), 0);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(7), 0);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(8), 0);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(8), 0);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(9), 0);
IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(9), 0);
IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(6), reg);
IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(7), 0);
IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(9), 0);
IPUV3_WRITE(sc, di0, IPU_DI_GENERAL, 0);
IPUV3_WRITE(sc, di0, IPU_DI_SYNC_AS_GEN, reg);
IPUV3_WRITE(sc, di0, IPU_DI_POL, DI_POL_DRDY_POLARITY_15);
IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
IPUV3_WRITE(sc, cm, IPU_CM_CONF, 0);
IPUV3_WRITE(sc, cm, IPU_CM_MEM_RST, CM_MEM_START | CM_MEM_EN);
IPUV3_WRITE(sc, dp, IPU_DP_GRAPH_WIND_CTRL_SYNC, 0x80 << 24);
IPUV3_WRITE(sc, dp, IPU_DP_COM_CONF_SYNC, DP_DP_GWAM_SYNC);
IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
IPUV3_WRITE(ioh, V3CR, status);
IPUV3_WRITE(sc, cpmem, addr + ((i % 5) * 0x4) +
IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);
IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_PRI_1, __BIT(CH_PANNEL_BG));
IPUV3_WRITE(sc, cm, IPU_CM_CH_DB_MODE_SEL_0, reg);
IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);
IPUV3_WRITE(sc, cm, IPU_CM_GPR, reg);
IPUV3_WRITE(sc, cm, IPU_CM_CUR_BUF_0, __BIT(CH_PANNEL_BG));