IO_TIMER1
#define PORT (IO_TIMER1+TIMER_CNTR0)
#define PORT (IO_TIMER1+TIMER_CNTR0)
isa_outb(IO_TIMER1 + TIMER_MODE,
isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256);
isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256);
if (bus_space_map(ia->ia_iot, IO_TIMER1, TIMER_IOSIZE, 0, &ioh))
ia->ia_io[0].ir_addr = IO_TIMER1;
ia->ia_io[0].ir_addr != IO_TIMER1))
isa_outb(IO_TIMER1 + TIMER_MODE,
isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256);
isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256);
outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
outb(IO_TIMER1 + TIMER_CNTR0, TIMER0_ROLLOVER % 256);
outb(IO_TIMER1 + TIMER_CNTR0, TIMER0_ROLLOVER / 256);
outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
lo = inb(IO_TIMER1 + TIMER_CNTR0);
hi = inb(IO_TIMER1 + TIMER_CNTR0);
outb(IO_TIMER1 + TIMER_MODE,
outb(IO_TIMER1 + TIMER_CNTR0, 0xff);
outb(IO_TIMER1 + TIMER_CNTR0, 0xff);
v1 = inb(IO_TIMER1+TIMER_CNTR0);
v1 |= inb(IO_TIMER1+TIMER_CNTR0) << 8;
v2 = inb(IO_TIMER1+TIMER_CNTR0);
v2 |= inb(IO_TIMER1+TIMER_CNTR0) << 8;
v3 = inb(IO_TIMER1+TIMER_CNTR0);
v3 |= inb(IO_TIMER1+TIMER_CNTR0) << 8;
outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
outb(IO_TIMER1+TIMER_CNTR0, tval % 256);
outb(IO_TIMER1+TIMER_CNTR0, tval / 256);
outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
rdval = inb(IO_TIMER1+TIMER_CNTR0);
rdval |= (inb(IO_TIMER1+TIMER_CNTR0) << 8);
outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
rdval = inb(IO_TIMER1+TIMER_CNTR0);
rdval |= (inb(IO_TIMER1+TIMER_CNTR0) << 8);
if (bus_space_map(ia->ia_iot, IO_TIMER1, 4, 0, &att_ioh))
ia->ia_io[0].ir_addr = IO_TIMER1;
if (bus_space_map(sc->sc_iot, IO_TIMER1, sc->sc_size, 0,
ia->ia_io[0].ir_addr != IO_TIMER1))