IO_ICU2 - NetBSD

sys/arch/algor/pci/pcib.c

170

if (bus_space_map(sc->sc_iot, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)

sys/arch/alpha/jensenio/jensenio_intr.c

375

static const int picaddr[2] = { IO_ICU1, IO_ICU2 };

sys/arch/alpha/pci/sio_pic.c

348

bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2))

sys/arch/arc/arc/c_isa.c

188

isa_outb(IO_ICU2, 0x0f);

sys/arch/arc/arc/c_isa.c

189

vector = isa_inb(IO_ICU2);

sys/arch/arc/isa/isabus.c

312

isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8);

sys/arch/arc/isa/isabus.c

428

isa_inb(IO_ICU2 + PIC_OCW1);

sys/arch/arc/isa/isabus.c

429

isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8);

sys/arch/arc/isa/isabus.c

430

isa_outb(IO_ICU2 + PIC_OCW2,

sys/arch/arc/isa/isabus.c

457

isa_inb(IO_ICU2 + PIC_OCW1);

sys/arch/arc/isa/isabus.c

459

isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8);

sys/arch/arc/isa/isabus.c

509

isa_outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);

sys/arch/arc/isa/isabus.c

511

isa_outb(IO_ICU2 + PIC_ICW2, 8);

sys/arch/arc/isa/isabus.c

513

isa_outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE));

sys/arch/arc/isa/isabus.c

515

isa_outb(IO_ICU2 + PIC_ICW4, ICW4_8086);

sys/arch/arc/isa/isabus.c

518

isa_outb(IO_ICU2 + PIC_OCW1, 0xff);

sys/arch/arc/isa/isabus.c

521

isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);

sys/arch/arc/isa/isabus.c

523

isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR);

sys/arch/arm/footbridge/isa/icu.h

54

outb(IO_ICU2 + 1, imen >> 8); \

sys/arch/arm/footbridge/isa/isa_machdep.c

140

outb(IO_ICU2, 0x11); /* reset; program device, four bytes */

sys/arch/arm/footbridge/isa/isa_machdep.c

141

outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */

sys/arch/arm/footbridge/isa/isa_machdep.c

142

outb(IO_ICU2+1, IRQ_SLAVE);

sys/arch/arm/footbridge/isa/isa_machdep.c

144

outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */

sys/arch/arm/footbridge/isa/isa_machdep.c

146

outb(IO_ICU2+1, 1); /* 8086 mode */

sys/arch/arm/footbridge/isa/isa_machdep.c

148

outb(IO_ICU2+1, 0xff); /* leave interrupts masked */

sys/arch/arm/footbridge/isa/isa_machdep.c

149

outb(IO_ICU2, 0x68); /* special mask mode (if available) */

sys/arch/arm/footbridge/isa/isa_machdep.c

150

outb(IO_ICU2, 0x0a); /* Read IRR by default. */

sys/arch/cobalt/cobalt/interrupt.c

179

bus_space_map(icu_bst, PCIB_BASE + IO_ICU2, IO_ICUSIZE, 0, &icu2_bsh);

sys/arch/evbmips/loongson/generic2e_machdep.c

305

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) =

sys/arch/evbmips/loongson/generic2e_machdep.c

307

ocw2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3);

sys/arch/evbmips/loongson/generic2e_machdep.c

577

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) =

sys/arch/evbmips/loongson/generic2e_machdep.c

579

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8);

sys/arch/evbmips/loongson/generic2e_machdep.c

580

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2);

sys/arch/evbmips/loongson/generic2e_machdep.c

581

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086;

sys/arch/evbmips/loongson/generic2e_machdep.c

583

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff;

sys/arch/evbmips/loongson/generic2e_machdep.c

585

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) =

sys/arch/evbmips/loongson/generic2e_machdep.c

588

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;

sys/arch/evbmips/loongson/isa_machdep.c

62

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = imr2;

sys/arch/evbmips/loongson/isa_machdep.c

75

(void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1);

sys/arch/evbmips/loongson/isa_machdep.c

76

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) =

sys/arch/evbmips/loongson/isa_machdep.c

79

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW2) =

sys/arch/evbmips/loongson/yeeloong_machdep.c

301

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff;

sys/arch/evbmips/loongson/yeeloong_machdep.c

302

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) =

sys/arch/evbmips/loongson/yeeloong_machdep.c

304

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8);

sys/arch/evbmips/loongson/yeeloong_machdep.c

305

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2);

sys/arch/evbmips/loongson/yeeloong_machdep.c

306

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086;

sys/arch/evbmips/loongson/yeeloong_machdep.c

309

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff;

sys/arch/evbmips/loongson/yeeloong_machdep.c

311

REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;

sys/arch/evbmips/loongson/yeeloong_machdep.c

312

(void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3);

sys/arch/evbmips/loongson/yeeloong_machdep.c

485

imr2 = 0xff & ~REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1);

sys/arch/evbmips/loongson/yeeloong_machdep.c

497

isr2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2);

sys/arch/evbmips/malta/pci/pcib.c

213

if (bus_space_map(sc->sc_iot, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)

sys/arch/ofppc/isa/isa_machdep.c

100

if (addr == IO_ICU2 || addr == IO_ICU2+1)

sys/arch/ofppc/isa/isa_machdep.c

102

addr-IO_ICU2, val);

sys/arch/ofppc/isa/isa_machdep.c

66

err = bus_space_map(&genppc_isa_io_space_tag, IO_ICU2, 2, 0,

sys/arch/ofppc/isa/isa_machdep.c

85

if (addr == IO_ICU2 || addr == IO_ICU2+1)

sys/arch/ofppc/isa/isa_machdep.c

87

addr-IO_ICU2);

sys/arch/powerpc/pic/i8259_common.c

108

isa_outb(IO_ICU2, 0x0c);

sys/arch/powerpc/pic/i8259_common.c

109

irq = (isa_inb(IO_ICU2) & 0x07) + 8;

sys/arch/powerpc/pic/i8259_common.c

57

isa_outb(IO_ICU2, 0x11); /* program device, four bytes */

sys/arch/powerpc/pic/i8259_common.c

58

isa_outb(IO_ICU2+1, 8); /* starting at this vector */

sys/arch/powerpc/pic/i8259_common.c

59

isa_outb(IO_ICU2+1, IRQ_SLAVE);

sys/arch/powerpc/pic/i8259_common.c

60

isa_outb(IO_ICU2+1, 1); /* 8086 mode */

sys/arch/powerpc/pic/i8259_common.c

61

isa_outb(IO_ICU2+1, 0xff); /* leave interrupts masked */

sys/arch/powerpc/pic/i8259_common.c

75

isa_outb(IO_ICU2+1, i8259->enable_mask >> 8);

sys/arch/powerpc/pic/i8259_common.c

86

isa_outb(IO_ICU2+1, i8259->enable_mask >> 8);

sys/arch/powerpc/pic/i8259_common.c

95

isa_outb(IO_ICU2, 0xe0 | (irq & 7));

sys/arch/shark/isa/icu.h

54

outb(IO_ICU2 + 1, imen >> 8); \

sys/arch/shark/isa/isa_shark_machdep.c

132

outb(IO_ICU2, 0x19); /* reset; four bytes, level triggered */

sys/arch/shark/isa/isa_shark_machdep.c

133

outb(IO_ICU2+1, ICU_OFFSET+8); /* int base + offset for master: not used */

sys/arch/shark/isa/isa_shark_machdep.c

134

outb(IO_ICU2+1, IRQ_SLAVE); /* who ami i? */

sys/arch/shark/isa/isa_shark_machdep.c

135

outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */

sys/arch/shark/isa/isa_shark_machdep.c

136

outb(IO_ICU2+1, 0xff); /* disable all interrupts */

sys/arch/shark/isa/isa_shark_machdep.c

137

outb(IO_ICU2, 0x68); /* special mask mode (if available) */

sys/arch/shark/isa/isa_shark_machdep.c

138

outb(IO_ICU2, 0x0a); /* Read IRR by default. */

sys/arch/x86/include/i8259.h

111

outb %al,$IO_ICU2 /* do the second ICU first */ ;\

sys/arch/x86/include/i8259.h

50

#define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))

sys/arch/x86/x86/i8259.c

167

outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_LTIM | ICW1_IC4);

sys/arch/x86/x86/i8259.c

171

outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);

sys/arch/x86/x86/i8259.c

174

outb(IO_ICU2 + PIC_ICW2, ICU_OFFSET + 8);

sys/arch/x86/x86/i8259.c

176

outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE));

sys/arch/x86/x86/i8259.c

179

outb(IO_ICU2 + PIC_ICW4, ICW4_AEOI | ICW4_8086);

sys/arch/x86/x86/i8259.c

182

outb(IO_ICU2 + PIC_ICW4, ICW4_8086);

sys/arch/x86/x86/i8259.c

185

outb(IO_ICU2 + PIC_OCW1, 0xff);

sys/arch/x86/x86/i8259.c

187

outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);

sys/arch/x86/x86/i8259.c

189

outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR);

sys/arch/x86/x86/i8259.c

203

port = IO_ICU2 + PIC_OCW1;

sys/arch/x86/x86/i8259.c

224

port = IO_ICU2 + PIC_OCW1;

sys/arch/x86/x86/i8259.c

252

outb(IO_ICU2 + PIC_OCW1, i8259_imen >> 8);

sys/arch/x86/x86/i8259.c

277

outb(IO_ICU2 + PIC_OCW1, i8259_imen >> 8);