IO_ICU1 - NetBSD

sys/arch/algor/pci/pcib.c

168

if (bus_space_map(sc->sc_iot, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)

sys/arch/alpha/jensenio/jensenio_intr.c

375

static const int picaddr[2] = { IO_ICU1, IO_ICU2 };

sys/arch/alpha/pci/sio_pic.c

347

if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) ||

sys/arch/arc/arc/c_isa.c

184

isa_outb(IO_ICU1, 0x0f); /* Poll */

sys/arch/arc/arc/c_isa.c

185

vector = isa_inb(IO_ICU1);

sys/arch/arc/isa/isabus.c

311

isa_outb(IO_ICU1 + PIC_OCW1, imen);

sys/arch/arc/isa/isabus.c

433

isa_outb(IO_ICU1,

sys/arch/arc/isa/isabus.c

436

isa_inb(IO_ICU1 + PIC_OCW1);

sys/arch/arc/isa/isabus.c

437

isa_outb(IO_ICU1 + PIC_OCW1, imen);

sys/arch/arc/isa/isabus.c

438

isa_outb(IO_ICU1 + PIC_OCW2,

sys/arch/arc/isa/isabus.c

456

isa_inb(IO_ICU1 + PIC_OCW1);

sys/arch/arc/isa/isabus.c

458

isa_outb(IO_ICU1 + PIC_OCW1, imen);

sys/arch/arc/isa/isabus.c

487

isa_outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);

sys/arch/arc/isa/isabus.c

489

isa_outb(IO_ICU1 + PIC_ICW2, 0);

sys/arch/arc/isa/isabus.c

491

isa_outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE));

sys/arch/arc/isa/isabus.c

493

isa_outb(IO_ICU1 + PIC_ICW4, ICW4_8086);

sys/arch/arc/isa/isabus.c

496

isa_outb(IO_ICU1 + PIC_OCW1, 0xff);

sys/arch/arc/isa/isabus.c

499

isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);

sys/arch/arc/isa/isabus.c

501

isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR);

sys/arch/arc/isa/isabus.c

504

isa_outb(IO_ICU1 + PIC_OCW2,

sys/arch/arm/footbridge/isa/icu.h

53

outb(IO_ICU1 + 1, imen); \

sys/arch/arm/footbridge/isa/isa_machdep.c

125

outb(IO_ICU1, 0x11); /* reset; program device, four bytes */

sys/arch/arm/footbridge/isa/isa_machdep.c

126

outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */

sys/arch/arm/footbridge/isa/isa_machdep.c

127

outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */

sys/arch/arm/footbridge/isa/isa_machdep.c

129

outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */

sys/arch/arm/footbridge/isa/isa_machdep.c

131

outb(IO_ICU1+1, 1); /* 8086 mode */

sys/arch/arm/footbridge/isa/isa_machdep.c

133

outb(IO_ICU1+1, 0xff); /* leave interrupts masked */

sys/arch/arm/footbridge/isa/isa_machdep.c

134

outb(IO_ICU1, 0x68); /* special mask mode (if available) */

sys/arch/arm/footbridge/isa/isa_machdep.c

135

outb(IO_ICU1, 0x0a); /* Read IRR by default. */

sys/arch/arm/footbridge/isa/isa_machdep.c

137

outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */

sys/arch/cobalt/cobalt/interrupt.c

178

bus_space_map(icu_bst, PCIB_BASE + IO_ICU1, IO_ICUSIZE, 0, &icu1_bsh);

sys/arch/evbmips/loongson/generic2e_machdep.c

296

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) =

sys/arch/evbmips/loongson/generic2e_machdep.c

298

ocw1 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3);

sys/arch/evbmips/loongson/generic2e_machdep.c

563

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW1) =

sys/arch/evbmips/loongson/generic2e_machdep.c

565

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW2) = ICW2_VECTOR(0);

sys/arch/evbmips/loongson/generic2e_machdep.c

566

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW3) = ICW3_CASCADE(2);

sys/arch/evbmips/loongson/generic2e_machdep.c

567

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW4) = ICW4_8086;

sys/arch/evbmips/loongson/generic2e_machdep.c

569

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1) = 0xff;

sys/arch/evbmips/loongson/generic2e_machdep.c

571

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) =

sys/arch/evbmips/loongson/generic2e_machdep.c

574

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;

sys/arch/evbmips/loongson/isa_machdep.c

64

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1) = imr1;

sys/arch/evbmips/loongson/isa_machdep.c

84

(void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1);

sys/arch/evbmips/loongson/isa_machdep.c

85

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1) =

sys/arch/evbmips/loongson/isa_machdep.c

88

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW2) =

sys/arch/evbmips/loongson/yeeloong_machdep.c

286

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1) = 0xff;

sys/arch/evbmips/loongson/yeeloong_machdep.c

287

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW1) =

sys/arch/evbmips/loongson/yeeloong_machdep.c

289

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW2) = ICW2_VECTOR(0);

sys/arch/evbmips/loongson/yeeloong_machdep.c

290

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW3) = ICW3_CASCADE(2);

sys/arch/evbmips/loongson/yeeloong_machdep.c

291

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW4) = ICW4_8086;

sys/arch/evbmips/loongson/yeeloong_machdep.c

294

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1) = 0xff;

sys/arch/evbmips/loongson/yeeloong_machdep.c

297

REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;

sys/arch/evbmips/loongson/yeeloong_machdep.c

298

(void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3);

sys/arch/evbmips/loongson/yeeloong_machdep.c

483

imr1 = 0xff & ~REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1);

sys/arch/evbmips/loongson/yeeloong_machdep.c

495

isr1 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU1);

sys/arch/evbmips/malta/pci/pcib.c

211

if (bus_space_map(sc->sc_iot, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)

sys/arch/ofppc/isa/isa_machdep.c

61

err = bus_space_map(&genppc_isa_io_space_tag, IO_ICU1, 2, 0,

sys/arch/ofppc/isa/isa_machdep.c

82

if (addr == IO_ICU1 || addr == IO_ICU1+1)

sys/arch/ofppc/isa/isa_machdep.c

84

addr-IO_ICU1);

sys/arch/ofppc/isa/isa_machdep.c

97

if (addr == IO_ICU1 || addr == IO_ICU1+1)

sys/arch/ofppc/isa/isa_machdep.c

99

addr-IO_ICU1, val);

sys/arch/powerpc/pic/i8259_common.c

105

isa_outb(IO_ICU1, 0x0c);

sys/arch/powerpc/pic/i8259_common.c

106

irq = isa_inb(IO_ICU1) & 0x07;

sys/arch/powerpc/pic/i8259_common.c

51

isa_outb(IO_ICU1, 0x11); /* program device, four bytes */

sys/arch/powerpc/pic/i8259_common.c

52

isa_outb(IO_ICU1+1, 0); /* starting at this vector */

sys/arch/powerpc/pic/i8259_common.c

53

isa_outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */

sys/arch/powerpc/pic/i8259_common.c

54

isa_outb(IO_ICU1+1, 1); /* 8086 mode */

sys/arch/powerpc/pic/i8259_common.c

55

isa_outb(IO_ICU1+1, 0xff); /* leave interrupts masked */

sys/arch/powerpc/pic/i8259_common.c

74

isa_outb(IO_ICU1+1, i8259->enable_mask);

sys/arch/powerpc/pic/i8259_common.c

85

isa_outb(IO_ICU1+1, i8259->enable_mask);

sys/arch/powerpc/pic/i8259_common.c

93

isa_outb(IO_ICU1, 0xe0 | irq);

sys/arch/powerpc/pic/i8259_common.c

96

isa_outb(IO_ICU1, 0xe0 | IRQ_SLAVE);

sys/arch/shark/isa/icu.h

53

outb(IO_ICU1 + 1, imen); \

sys/arch/shark/isa/isa_shark_machdep.c

124

outb(IO_ICU1, 0x19); /* reset; four bytes, level triggered */

sys/arch/shark/isa/isa_shark_machdep.c

125

outb(IO_ICU1+1, ICU_OFFSET); /* int base: not used */

sys/arch/shark/isa/isa_shark_machdep.c

126

outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */

sys/arch/shark/isa/isa_shark_machdep.c

127

outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */

sys/arch/shark/isa/isa_shark_machdep.c

128

outb(IO_ICU1+1, 0xff); /* disable all interrupts */

sys/arch/shark/isa/isa_shark_machdep.c

129

outb(IO_ICU1, 0x68); /* special mask mode (if available) */

sys/arch/shark/isa/isa_shark_machdep.c

130

outb(IO_ICU1, 0x0a); /* Read IRR, not ISR */

sys/arch/x86/include/i8259.h

103

outb %al,$IO_ICU1

sys/arch/x86/include/i8259.h

113

outb %al,$IO_ICU1

sys/arch/x86/include/i8259.h

50

#define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))

sys/arch/x86/include/i8259.h

92

outb %al,$IO_ICU1

sys/arch/x86/x86/i8259.c

133

outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_LTIM | ICW1_IC4);

sys/arch/x86/x86/i8259.c

137

outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4);

sys/arch/x86/x86/i8259.c

140

outb(IO_ICU1 + PIC_ICW2, ICU_OFFSET);

sys/arch/x86/x86/i8259.c

142

outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE));

sys/arch/x86/x86/i8259.c

146

outb(IO_ICU1 + PIC_ICW4, ICW4_AEOI | ICW4_8086);

sys/arch/x86/x86/i8259.c

149

outb(IO_ICU1 + PIC_ICW4, ICW4_8086);

sys/arch/x86/x86/i8259.c

152

outb(IO_ICU1 + PIC_OCW1, 0xff);

sys/arch/x86/x86/i8259.c

154

outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM);

sys/arch/x86/x86/i8259.c

156

outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR);

sys/arch/x86/x86/i8259.c

159

outb(IO_ICU1 + PIC_OCW2, OCW2_SELECT | OCW2_R | OCW2_SL |

sys/arch/x86/x86/i8259.c

206

port = IO_ICU1 + PIC_OCW1;

sys/arch/x86/x86/i8259.c

227

port = IO_ICU1 + PIC_OCW1;

sys/arch/x86/x86/i8259.c

251

outb(IO_ICU1 + PIC_OCW1, i8259_imen);

sys/arch/x86/x86/i8259.c

276

outb(IO_ICU1 + PIC_OCW1, i8259_imen);