sys/arch/arm/sunxi/sunxi_intc.c

100

INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]);

sys/arch/arm/sunxi/sunxi_intc.c

111

INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]);

sys/arch/arm/sunxi/sunxi_intc.c

254

INTC_WRITE(sc, INTC_MASK_REG(i), ~0U);

sys/arch/ews4800mips/ews4800mips/tr2a_intr.c

116

*INTC_MASK_REG = 0;

sys/arch/ews4800mips/ews4800mips/tr2a_intr.c

144

*INTC_MASK_REG |= ic->mask;

sys/arch/ews4800mips/ews4800mips/tr2a_intr.c

164

*INTC_MASK_REG &= ~ic->mask;

sys/arch/ews4800mips/ews4800mips/tr2a_intr.c

180

intc_cause = *INTC_STATUS_REG & *INTC_MASK_REG;

sys/arch/ews4800mips/ews4800mips/tr2a_intr.c

290

intc_cause = *INTC_STATUS_REG & *INTC_MASK_REG;

sys/arch/ews4800mips/ews4800mips/tr2a_intr.c

299

*INTC_MASK_REG |= INTC_INT5;