sys/arch/arm/broadcom/bcm53xx_cca.c

201

uint32_t v = bcmcca_read_4(sc, IDM_BASE + APBX_IDM_IO_CONTROL_DIRECT);

sys/arch/arm/broadcom/bcm53xx_cca.c

204

bcmcca_write_4(sc, IDM_BASE + APBX_IDM_IO_CONTROL_DIRECT, v);

sys/arch/arm/broadcom/bcm53xx_idm.c

121

bus_size_t o = IDM_BASE + idm->idm_offset + IDM_RESET_CONTROL;

sys/arch/arm/broadcom/bcm53xx_idm.c

67

IDM_BASE + IDM_AMAC0_BASE,

sys/arch/arm/broadcom/bcm53xx_idm.c

68

IDM_BASE + IDM_AMAC1_BASE,

sys/arch/arm/broadcom/bcm53xx_idm.c

69

IDM_BASE + IDM_AMAC2_BASE,

sys/arch/arm/broadcom/bcm53xx_idm.c

70

IDM_BASE + IDM_AMAC3_BASE,

sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c

409

IDM_BASE + IDM_APBX_BASE + IDM_IO_CONTROL_DIRECT);

sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c

412

IDM_BASE + IDM_APBX_BASE + IDM_IO_CONTROL_DIRECT, v);