ICU_NO_REG_W
#define VR4122_AIUINT_REG_W ICU_NO_REG_W /* Level2 AIU intr reg */
#define VR4122_MAIUINT_REG_W ICU_NO_REG_W /* Level2 Mask AIU intr reg */
#define VR4122_KIUINT_REG_W ICU_NO_REG_W /* Level2 KIU intr reg */
#define VR4122_MKIUINT_REG_W ICU_NO_REG_W /* Level2 Mask KIU intr reg */
#define VR4181_GIUINT_L_REG_W ICU_NO_REG_W /* Level2 GIU intr reg Low */
#define VR4181_MGIUINT_L_REG_W ICU_NO_REG_W /* Level2 Mask GIU intr reg Low */
#define VR4181_DSIUINT_REG_W ICU_NO_REG_W /* Level2 DSIU intr reg */
#define VR4181_MDSIUINT_REG_W ICU_NO_REG_W /* Level2 Mask DSIU intr reg */
#define VR4181_GIUINT_H_REG_W ICU_NO_REG_W /* Level2 GIU intr reg High */
#define VR4181_MGIUINT_H_REG_W ICU_NO_REG_W /* Level2 Mask GIU intr reg High */
#define VR4181_FIRINT_REG_W ICU_NO_REG_W /* Level2 FIR intr reg */
#define VR4181_MFIRINT_REG_W ICU_NO_REG_W /* Level2 Mask FIR intr reg */
#define VR4102_PCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr reg */
#define VR4102_MPCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr mask */
#define VR4181_PCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr reg */
#define VR4181_MPCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr mask */
#define VR4102_SCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr reg */
#define VR4102_MSCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr mask */
#define VR4181_SCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr reg */
#define VR4181_MSCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr mask */
#define VR4102_CSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr reg */
#define VR4102_MCSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr mask */
#define VR4181_CSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr reg */
#define VR4181_MCSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr mask */
#define VR4102_BCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr reg */
#define VR4102_MBCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr mask */
#define VR4181_BCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr reg */
#define VR4181_MBCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr mask */