sys/dev/pci/if_ixlreg.h
1001
#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1003
#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1005
#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1007
#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1009
#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
101
#define I40E_GL_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT)
sys/dev/pci/if_ixlreg.h
1011
#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1013
#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1015
#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1018
#define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
1020
#define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_QUEUE_0_SHIFT)
sys/dev/pci/if_ixlreg.h
1022
#define I40E_PFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_QUEUE_1_SHIFT)
sys/dev/pci/if_ixlreg.h
1024
#define I40E_PFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_QUEUE_2_SHIFT)
sys/dev/pci/if_ixlreg.h
1026
#define I40E_PFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_QUEUE_3_SHIFT)
sys/dev/pci/if_ixlreg.h
1028
#define I40E_PFINT_ICR0_QUEUE_4_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_QUEUE_4_SHIFT)
sys/dev/pci/if_ixlreg.h
1030
#define I40E_PFINT_ICR0_QUEUE_5_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_QUEUE_5_SHIFT)
sys/dev/pci/if_ixlreg.h
1032
#define I40E_PFINT_ICR0_QUEUE_6_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_QUEUE_6_SHIFT)
sys/dev/pci/if_ixlreg.h
1034
#define I40E_PFINT_ICR0_QUEUE_7_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_QUEUE_7_SHIFT)
sys/dev/pci/if_ixlreg.h
1036
#define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ECC_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1038
#define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_MAL_DETECT_SHIFT)
sys/dev/pci/if_ixlreg.h
104
#define I40E_PF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT)
sys/dev/pci/if_ixlreg.h
1040
#define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_GRST_SHIFT)
sys/dev/pci/if_ixlreg.h
1042
#define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT)
sys/dev/pci/if_ixlreg.h
1044
#define I40E_PFINT_ICR0_GPIO_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_GPIO_SHIFT)
sys/dev/pci/if_ixlreg.h
1046
#define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_TIMESYNC_SHIFT)
sys/dev/pci/if_ixlreg.h
1048
#define I40E_PFINT_ICR0_STORM_DETECT_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_STORM_DETECT_SHIFT)
sys/dev/pci/if_ixlreg.h
1050
#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
1052
#define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_HMC_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1054
#define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_PE_CRITERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1056
#define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_VFLR_SHIFT)
sys/dev/pci/if_ixlreg.h
1058
#define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ADMINQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1060
#define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_SWINT_SHIFT)
sys/dev/pci/if_ixlreg.h
1063
#define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1065
#define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT)
sys/dev/pci/if_ixlreg.h
1067
#define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_GRST_SHIFT)
sys/dev/pci/if_ixlreg.h
1069
#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT)
sys/dev/pci/if_ixlreg.h
107
#define I40E_PF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1071
#define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_GPIO_SHIFT)
sys/dev/pci/if_ixlreg.h
1073
#define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT)
sys/dev/pci/if_ixlreg.h
1075
#define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT)
sys/dev/pci/if_ixlreg.h
1077
#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
1079
#define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1081
#define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1083
#define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_VFLR_SHIFT)
sys/dev/pci/if_ixlreg.h
1085
#define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1087
#define I40E_PFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1U, I40E_PFINT_ICR0_ENA_RSVD_SHIFT)
sys/dev/pci/if_ixlreg.h
1091
#define I40E_PFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1095
#define I40E_PFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1098
#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
110
#define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
sys/dev/pci/if_ixlreg.h
1100
#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1104
#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1106
#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1109
#define I40E_PFINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1111
#define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_RATE0_INTRL_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1115
#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1117
#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1120
#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1124
#define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1126
#define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1128
#define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
113
#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
1130
#define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1132
#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1134
#define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1U, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1136
#define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1U, I40E_QINT_RQCTL_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
1140
#define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1142
#define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1144
#define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1146
#define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1148
#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
115
#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1U, I40E_PF_ARQLEN_ARQVFE_SHIFT)
sys/dev/pci/if_ixlreg.h
1150
#define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1U, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1152
#define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1U, I40E_QINT_TQCTL_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
1156
#define I40E_VFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL0_INTENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1158
#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT)
sys/dev/pci/if_ixlreg.h
1160
#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
sys/dev/pci/if_ixlreg.h
1162
#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1164
#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1166
#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1168
#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
117
#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1U, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
sys/dev/pci/if_ixlreg.h
1170
#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT)
sys/dev/pci/if_ixlreg.h
1174
#define I40E_VFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN_INTENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1176
#define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT)
sys/dev/pci/if_ixlreg.h
1178
#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
sys/dev/pci/if_ixlreg.h
1180
#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1182
#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1184
#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1186
#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1188
#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT)
sys/dev/pci/if_ixlreg.h
119
#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1U, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
sys/dev/pci/if_ixlreg.h
1192
#define I40E_VFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
1194
#define I40E_VFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_QUEUE_0_SHIFT)
sys/dev/pci/if_ixlreg.h
1196
#define I40E_VFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_QUEUE_1_SHIFT)
sys/dev/pci/if_ixlreg.h
1198
#define I40E_VFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_QUEUE_2_SHIFT)
sys/dev/pci/if_ixlreg.h
1200
#define I40E_VFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_QUEUE_3_SHIFT)
sys/dev/pci/if_ixlreg.h
1202
#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
1204
#define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_ADMINQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1206
#define I40E_VFINT_ICR0_SWINT_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_SWINT_SHIFT)
sys/dev/pci/if_ixlreg.h
121
#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1U, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
1210
#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
1212
#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1214
#define I40E_VFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_ENA_RSVD_SHIFT)
sys/dev/pci/if_ixlreg.h
1218
#define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1222
#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1226
#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1230
#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1232
#define I40E_VPINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_AEQCTL_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1234
#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1236
#define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1U, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1238
#define I40E_VPINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1U, I40E_VPINT_AEQCTL_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
124
#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
sys/dev/pci/if_ixlreg.h
1242
#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1244
#define I40E_VPINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1246
#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1248
#define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1250
#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1252
#define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1U, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1254
#define I40E_VPINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1U, I40E_VPINT_CEQCTL_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
1258
#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1260
#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1264
#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1266
#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
127
#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)
sys/dev/pci/if_ixlreg.h
1270
#define I40E_VPINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1272
#define I40E_VPINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1U, I40E_VPINT_RATE0_INTRL_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1276
#define I40E_VPINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1278
#define I40E_VPINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1U, I40E_VPINT_RATEN_INTRL_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1281
#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK I40E_MASK(0x1U, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1283
#define I40E_GL_RDPU_CNTRL_ECO_MASK I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT)
sys/dev/pci/if_ixlreg.h
1286
#define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1U, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
1289
#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT)
sys/dev/pci/if_ixlreg.h
1292
#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT)
sys/dev/pci/if_ixlreg.h
1295
#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT)
sys/dev/pci/if_ixlreg.h
1299
#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)
sys/dev/pci/if_ixlreg.h
130
#define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1301
#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1U, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT)
sys/dev/pci/if_ixlreg.h
1303
#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1U, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
sys/dev/pci/if_ixlreg.h
1305
#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1U, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
sys/dev/pci/if_ixlreg.h
1308
#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1310
#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1312
#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1U, I40E_PFLAN_QALLOC_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
1316
#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1U, I40E_QRX_ENA_QENA_REQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1318
#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1U, I40E_QRX_ENA_FAST_QDIS_SHIFT)
sys/dev/pci/if_ixlreg.h
1320
#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1U, I40E_QRX_ENA_QENA_STAT_SHIFT)
sys/dev/pci/if_ixlreg.h
1324
#define I40E_QRX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
1328
#define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT)
sys/dev/pci/if_ixlreg.h
133
#define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)
sys/dev/pci/if_ixlreg.h
1330
#define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1332
#define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
1336
#define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1U, I40E_QTX_ENA_QENA_REQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1338
#define I40E_QTX_ENA_FAST_QDIS_MASK I40E_MASK(0x1U, I40E_QTX_ENA_FAST_QDIS_SHIFT)
sys/dev/pci/if_ixlreg.h
1340
#define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1U, I40E_QTX_ENA_QENA_STAT_SHIFT)
sys/dev/pci/if_ixlreg.h
1344
#define I40E_QTX_HEAD_HEAD_MASK I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT)
sys/dev/pci/if_ixlreg.h
1346
#define I40E_QTX_HEAD_RS_PENDING_MASK I40E_MASK(0x1U, I40E_QTX_HEAD_RS_PENDING_SHIFT)
sys/dev/pci/if_ixlreg.h
1350
#define I40E_QTX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
1354
#define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1U, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1358
#define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT)
sys/dev/pci/if_ixlreg.h
136
#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
1362
#define I40E_VSILAN_QBASE_VSIBASE_MASK I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
1364
#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1U, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
1368
#define I40E_VSILAN_QTABLE_QINDEX_0_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)
sys/dev/pci/if_ixlreg.h
1370
#define I40E_VSILAN_QTABLE_QINDEX_1_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT)
sys/dev/pci/if_ixlreg.h
1373
#define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)
sys/dev/pci/if_ixlreg.h
1375
#define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFFU, I40E_PRTGL_SAH_MFS_SHIFT)
sys/dev/pci/if_ixlreg.h
1378
#define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)
sys/dev/pci/if_ixlreg.h
138
#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1U, I40E_PF_ATQLEN_ATQVFE_SHIFT)
sys/dev/pci/if_ixlreg.h
1381
#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK I40E_MASK(0x1U, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT)
sys/dev/pci/if_ixlreg.h
1384
#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1U, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT)
sys/dev/pci/if_ixlreg.h
1387
#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1U, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT)
sys/dev/pci/if_ixlreg.h
1390
#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK I40E_MASK(0x1U, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT)
sys/dev/pci/if_ixlreg.h
1393
#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT)
sys/dev/pci/if_ixlreg.h
1396
#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT)
sys/dev/pci/if_ixlreg.h
1399
#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
140
#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1U, I40E_PF_ATQLEN_ATQOVFL_SHIFT)
sys/dev/pci/if_ixlreg.h
1402
#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT)
sys/dev/pci/if_ixlreg.h
1405
#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT)
sys/dev/pci/if_ixlreg.h
1408
#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
1412
#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT)
sys/dev/pci/if_ixlreg.h
1416
#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)
sys/dev/pci/if_ixlreg.h
1419
#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT)
sys/dev/pci/if_ixlreg.h
142
#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1U, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
sys/dev/pci/if_ixlreg.h
1422
#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT)
sys/dev/pci/if_ixlreg.h
1425
#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT)
sys/dev/pci/if_ixlreg.h
1427
#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT)
sys/dev/pci/if_ixlreg.h
1429
#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT)
sys/dev/pci/if_ixlreg.h
1431
#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT)
sys/dev/pci/if_ixlreg.h
1433
#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT)
sys/dev/pci/if_ixlreg.h
1435
#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT)
sys/dev/pci/if_ixlreg.h
1437
#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT)
sys/dev/pci/if_ixlreg.h
1439
#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT)
sys/dev/pci/if_ixlreg.h
144
#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1U, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
1442
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT)
sys/dev/pci/if_ixlreg.h
1444
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT)
sys/dev/pci/if_ixlreg.h
1446
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT)
sys/dev/pci/if_ixlreg.h
1448
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT)
sys/dev/pci/if_ixlreg.h
1450
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT)
sys/dev/pci/if_ixlreg.h
1452
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT)
sys/dev/pci/if_ixlreg.h
1454
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)
sys/dev/pci/if_ixlreg.h
1456
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
sys/dev/pci/if_ixlreg.h
1459
#define I40E_GL_FWRESETCNT_FWRESETCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
1462
#define I40E_GL_MNG_FWSM_FW_MODES_MASK I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
sys/dev/pci/if_ixlreg.h
1464
#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK I40E_MASK(0x1U, I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT)
sys/dev/pci/if_ixlreg.h
1466
#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK I40E_MASK(0xF, I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT)
sys/dev/pci/if_ixlreg.h
1468
#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK I40E_MASK(0x1U, I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
147
#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
sys/dev/pci/if_ixlreg.h
1470
#define I40E_GL_MNG_FWSM_RESET_CNT_MASK I40E_MASK(0x7, I40E_GL_MNG_FWSM_RESET_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
1472
#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK I40E_MASK(0x3F, I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT)
sys/dev/pci/if_ixlreg.h
1474
#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK I40E_MASK(0x1U, I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1476
#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK I40E_MASK(0x1U, I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1478
#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK I40E_MASK(0x1U, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1480
#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK I40E_MASK(0x1U, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
1483
#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK I40E_MASK(0x1U, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1487
#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT)
sys/dev/pci/if_ixlreg.h
1490
#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT)
sys/dev/pci/if_ixlreg.h
1494
#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
1497
#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT)
sys/dev/pci/if_ixlreg.h
1499
#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT)
sys/dev/pci/if_ixlreg.h
1501
#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1503
#define I40E_PRT_MNG_MANC_RCV_ALL_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MANC_RCV_ALL_SHIFT)
sys/dev/pci/if_ixlreg.h
1505
#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1507
#define I40E_PRT_MNG_MANC_NET_TYPE_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MANC_NET_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1509
#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT)
sys/dev/pci/if_ixlreg.h
151
#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)
sys/dev/pci/if_ixlreg.h
1511
#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT)
sys/dev/pci/if_ixlreg.h
1515
#define I40E_PRT_MNG_MAVTV_VID_MASK I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT)
sys/dev/pci/if_ixlreg.h
1519
#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT)
sys/dev/pci/if_ixlreg.h
1521
#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT)
sys/dev/pci/if_ixlreg.h
1523
#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT)
sys/dev/pci/if_ixlreg.h
1525
#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT)
sys/dev/pci/if_ixlreg.h
1527
#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT)
sys/dev/pci/if_ixlreg.h
1529
#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1531
#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1533
#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT)
sys/dev/pci/if_ixlreg.h
1535
#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1537
#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1539
#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1541
#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1543
#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1547
#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT)
sys/dev/pci/if_ixlreg.h
1549
#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
155
#define I40E_VF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1551
#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1553
#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT)
sys/dev/pci/if_ixlreg.h
1555
#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1557
#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1559
#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1561
#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT)
sys/dev/pci/if_ixlreg.h
1563
#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT)
sys/dev/pci/if_ixlreg.h
1565
#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT)
sys/dev/pci/if_ixlreg.h
1567
#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT)
sys/dev/pci/if_ixlreg.h
1571
#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)
sys/dev/pci/if_ixlreg.h
1573
#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK I40E_MASK(0xFFFFU, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
sys/dev/pci/if_ixlreg.h
1577
#define I40E_PRT_MNG_METF_ETYPE_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1579
#define I40E_PRT_MNG_METF_POLARITY_MASK I40E_MASK(0x1U, I40E_PRT_MNG_METF_POLARITY_SHIFT)
sys/dev/pci/if_ixlreg.h
1583
#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT)
sys/dev/pci/if_ixlreg.h
1585
#define I40E_PRT_MNG_MFUTP_UDP_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MFUTP_UDP_SHIFT)
sys/dev/pci/if_ixlreg.h
1587
#define I40E_PRT_MNG_MFUTP_TCP_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MFUTP_TCP_SHIFT)
sys/dev/pci/if_ixlreg.h
1589
#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT)
sys/dev/pci/if_ixlreg.h
159
#define I40E_VF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT)
sys/dev/pci/if_ixlreg.h
1593
#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT)
sys/dev/pci/if_ixlreg.h
1597
#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT)
sys/dev/pci/if_ixlreg.h
1601
#define I40E_PRT_MNG_MMAH_MMAH_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT)
sys/dev/pci/if_ixlreg.h
1605
#define I40E_PRT_MNG_MMAL_MMAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1608
#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT)
sys/dev/pci/if_ixlreg.h
1611
#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT)
sys/dev/pci/if_ixlreg.h
1613
#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT)
sys/dev/pci/if_ixlreg.h
1615
#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT)
sys/dev/pci/if_ixlreg.h
1617
#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT)
sys/dev/pci/if_ixlreg.h
1619
#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
1621
#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
1623
#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
1625
#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK I40E_MASK(0x1U, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
1629
#define I40E_MSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT)
sys/dev/pci/if_ixlreg.h
163
#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
1633
#define I40E_MSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT)
sys/dev/pci/if_ixlreg.h
1635
#define I40E_MSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT)
sys/dev/pci/if_ixlreg.h
1639
#define I40E_MSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT)
sys/dev/pci/if_ixlreg.h
1643
#define I40E_MSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT)
sys/dev/pci/if_ixlreg.h
1647
#define I40E_MSIX_TVCTRL_MASK_MASK I40E_MASK(0x1U, I40E_MSIX_TVCTRL_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
165
#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1U, I40E_VF_ARQLEN_ARQVFE_SHIFT)
sys/dev/pci/if_ixlreg.h
1651
#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)
sys/dev/pci/if_ixlreg.h
1655
#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
sys/dev/pci/if_ixlreg.h
1657
#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
sys/dev/pci/if_ixlreg.h
1661
#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
sys/dev/pci/if_ixlreg.h
1665
#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
sys/dev/pci/if_ixlreg.h
1669
#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1U, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
167
#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1U, I40E_VF_ARQLEN_ARQOVFL_SHIFT)
sys/dev/pci/if_ixlreg.h
1672
#define I40E_GLNVM_FLA_FL_SCK_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_FL_SCK_SHIFT)
sys/dev/pci/if_ixlreg.h
1674
#define I40E_GLNVM_FLA_FL_CE_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_FL_CE_SHIFT)
sys/dev/pci/if_ixlreg.h
1676
#define I40E_GLNVM_FLA_FL_SI_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_FL_SI_SHIFT)
sys/dev/pci/if_ixlreg.h
1678
#define I40E_GLNVM_FLA_FL_SO_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_FL_SO_SHIFT)
sys/dev/pci/if_ixlreg.h
1680
#define I40E_GLNVM_FLA_FL_REQ_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_FL_REQ_SHIFT)
sys/dev/pci/if_ixlreg.h
1682
#define I40E_GLNVM_FLA_FL_GNT_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_FL_GNT_SHIFT)
sys/dev/pci/if_ixlreg.h
1684
#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_LOCKED_SHIFT)
sys/dev/pci/if_ixlreg.h
1686
#define I40E_GLNVM_FLA_FL_SADDR_MASK I40E_MASK(0x7FF, I40E_GLNVM_FLA_FL_SADDR_SHIFT)
sys/dev/pci/if_ixlreg.h
1688
#define I40E_GLNVM_FLA_FL_BUSY_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_FL_BUSY_SHIFT)
sys/dev/pci/if_ixlreg.h
169
#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1U, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
sys/dev/pci/if_ixlreg.h
1690
#define I40E_GLNVM_FLA_FL_DER_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_FL_DER_SHIFT)
sys/dev/pci/if_ixlreg.h
1693
#define I40E_GLNVM_FLASHID_FLASHID_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT)
sys/dev/pci/if_ixlreg.h
1695
#define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK I40E_MASK(0x1U, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT)
sys/dev/pci/if_ixlreg.h
1698
#define I40E_GLNVM_GENS_NVM_PRES_MASK I40E_MASK(0x1U, I40E_GLNVM_GENS_NVM_PRES_SHIFT)
sys/dev/pci/if_ixlreg.h
1700
#define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
1702
#define I40E_GLNVM_GENS_BANK1VAL_MASK I40E_MASK(0x1U, I40E_GLNVM_GENS_BANK1VAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1704
#define I40E_GLNVM_GENS_ALT_PRST_MASK I40E_MASK(0x1U, I40E_GLNVM_GENS_ALT_PRST_SHIFT)
sys/dev/pci/if_ixlreg.h
1706
#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK I40E_MASK(0x1U, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT)
sys/dev/pci/if_ixlreg.h
171
#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1U, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
1710
#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT)
sys/dev/pci/if_ixlreg.h
1713
#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1U, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)
sys/dev/pci/if_ixlreg.h
1715
#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT)
sys/dev/pci/if_ixlreg.h
1717
#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1U, I40E_GLNVM_SRCTL_WRITE_SHIFT)
sys/dev/pci/if_ixlreg.h
1719
#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1U, I40E_GLNVM_SRCTL_START_SHIFT)
sys/dev/pci/if_ixlreg.h
1721
#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_SRCTL_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1724
#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
sys/dev/pci/if_ixlreg.h
1726
#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFFU, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
sys/dev/pci/if_ixlreg.h
1729
#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1731
#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1733
#define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1735
#define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1737
#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1739
#define I40E_GLNVM_ULD_CONF_POR_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1741
#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1743
#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1745
#define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
1747
#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
175
#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)
sys/dev/pci/if_ixlreg.h
1750
#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT)
sys/dev/pci/if_ixlreg.h
1753
#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT)
sys/dev/pci/if_ixlreg.h
1756
#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1759
#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT)
sys/dev/pci/if_ixlreg.h
1761
#define I40E_GLPCI_CAPSUP_LTR_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_LTR_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1763
#define I40E_GLPCI_CAPSUP_TPH_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_TPH_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1765
#define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1767
#define I40E_GLPCI_CAPSUP_IOV_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_IOV_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1769
#define I40E_GLPCI_CAPSUP_ACS_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_ACS_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1771
#define I40E_GLPCI_CAPSUP_SEC_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_SEC_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1773
#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1775
#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1777
#define I40E_GLPCI_CAPSUP_IDO_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_IDO_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1779
#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
1781
#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1783
#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
1785
#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
1788
#define I40E_GLPCI_CNF_FLEX10_MASK I40E_MASK(0x1U, I40E_GLPCI_CNF_FLEX10_SHIFT)
sys/dev/pci/if_ixlreg.h
179
#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)
sys/dev/pci/if_ixlreg.h
1790
#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1793
#define I40E_GLPCI_CNF2_RO_DIS_MASK I40E_MASK(0x1U, I40E_GLPCI_CNF2_RO_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
1795
#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK I40E_MASK(0x1U, I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
1797
#define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)
sys/dev/pci/if_ixlreg.h
1799
#define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)
sys/dev/pci/if_ixlreg.h
1802
#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT)
sys/dev/pci/if_ixlreg.h
1805
#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT)
sys/dev/pci/if_ixlreg.h
1807
#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT)
sys/dev/pci/if_ixlreg.h
1809
#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT)
sys/dev/pci/if_ixlreg.h
1811
#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT)
sys/dev/pci/if_ixlreg.h
1813
#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT)
sys/dev/pci/if_ixlreg.h
1815
#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT)
sys/dev/pci/if_ixlreg.h
1817
#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT)
sys/dev/pci/if_ixlreg.h
1819
#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT)
sys/dev/pci/if_ixlreg.h
1821
#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1823
#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT)
sys/dev/pci/if_ixlreg.h
1825
#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1827
#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT)
sys/dev/pci/if_ixlreg.h
1829
#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
183
#define I40E_VF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT)
sys/dev/pci/if_ixlreg.h
1831
#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT)
sys/dev/pci/if_ixlreg.h
1833
#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT)
sys/dev/pci/if_ixlreg.h
1835
#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK I40E_MASK(0x1U, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT)
sys/dev/pci/if_ixlreg.h
1838
#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT)
sys/dev/pci/if_ixlreg.h
1840
#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT)
sys/dev/pci/if_ixlreg.h
1842
#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT)
sys/dev/pci/if_ixlreg.h
1844
#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT)
sys/dev/pci/if_ixlreg.h
1848
#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)
sys/dev/pci/if_ixlreg.h
1850
#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
sys/dev/pci/if_ixlreg.h
1854
#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
sys/dev/pci/if_ixlreg.h
1857
#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1U, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
sys/dev/pci/if_ixlreg.h
1859
#define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1U, I40E_GLPCI_LBARCTRL_BAR32_SHIFT)
sys/dev/pci/if_ixlreg.h
1861
#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1U, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT)
sys/dev/pci/if_ixlreg.h
1863
#define I40E_GLPCI_LBARCTRL_RSVD_4_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT)
sys/dev/pci/if_ixlreg.h
1865
#define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
1867
#define I40E_GLPCI_LBARCTRL_RSVD_10_MASK I40E_MASK(0x1U, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT)
sys/dev/pci/if_ixlreg.h
1869
#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
187
#define I40E_VF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT)
sys/dev/pci/if_ixlreg.h
1872
#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT)
sys/dev/pci/if_ixlreg.h
1874
#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT)
sys/dev/pci/if_ixlreg.h
1876
#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT)
sys/dev/pci/if_ixlreg.h
1879
#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
sys/dev/pci/if_ixlreg.h
1882
#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
sys/dev/pci/if_ixlreg.h
1885
#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)
sys/dev/pci/if_ixlreg.h
1887
#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT)
sys/dev/pci/if_ixlreg.h
1890
#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)
sys/dev/pci/if_ixlreg.h
1892
#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)
sys/dev/pci/if_ixlreg.h
1895
#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT)
sys/dev/pci/if_ixlreg.h
1897
#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT)
sys/dev/pci/if_ixlreg.h
1899
#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT)
sys/dev/pci/if_ixlreg.h
1901
#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT)
sys/dev/pci/if_ixlreg.h
1903
#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT)
sys/dev/pci/if_ixlreg.h
1905
#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK I40E_MASK(0x1U, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT)
sys/dev/pci/if_ixlreg.h
1907
#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT)
sys/dev/pci/if_ixlreg.h
191
#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
1910
#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT)
sys/dev/pci/if_ixlreg.h
1912
#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT)
sys/dev/pci/if_ixlreg.h
1915
#define I40E_GLPCI_PWRDATA_D0_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT)
sys/dev/pci/if_ixlreg.h
1917
#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT)
sys/dev/pci/if_ixlreg.h
1919
#define I40E_GLPCI_PWRDATA_D3_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT)
sys/dev/pci/if_ixlreg.h
1921
#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT)
sys/dev/pci/if_ixlreg.h
1924
#define I40E_GLPCI_REVID_NVM_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT)
sys/dev/pci/if_ixlreg.h
1927
#define I40E_GLPCI_SERH_SER_NUM_H_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT)
sys/dev/pci/if_ixlreg.h
193
#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1U, I40E_VF_ATQLEN_ATQVFE_SHIFT)
sys/dev/pci/if_ixlreg.h
1930
#define I40E_GLPCI_SERL_SER_NUM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT)
sys/dev/pci/if_ixlreg.h
1933
#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)
sys/dev/pci/if_ixlreg.h
1936
#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT)
sys/dev/pci/if_ixlreg.h
1939
#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
1942
#define I40E_GLPCI_UPADD_ADDRESS_MASK I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT)
sys/dev/pci/if_ixlreg.h
1945
#define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT)
sys/dev/pci/if_ixlreg.h
1948
#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1U, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
sys/dev/pci/if_ixlreg.h
195
#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1U, I40E_VF_ATQLEN_ATQOVFL_SHIFT)
sys/dev/pci/if_ixlreg.h
1950
#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1U, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
1953
#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT)
sys/dev/pci/if_ixlreg.h
1955
#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT)
sys/dev/pci/if_ixlreg.h
1958
#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
sys/dev/pci/if_ixlreg.h
1960
#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT)
sys/dev/pci/if_ixlreg.h
1962
#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT)
sys/dev/pci/if_ixlreg.h
1965
#define I40E_PF_PCI_CIAA_ADDRESS_MASK I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT)
sys/dev/pci/if_ixlreg.h
1967
#define I40E_PF_PCI_CIAA_VF_NUM_MASK I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
197
#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1U, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
sys/dev/pci/if_ixlreg.h
1970
#define I40E_PF_PCI_CIAD_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT)
sys/dev/pci/if_ixlreg.h
1973
#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK I40E_MASK(0x1U, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT)
sys/dev/pci/if_ixlreg.h
1975
#define I40E_PFPCI_CLASS_RESERVED_1_MASK I40E_MASK(0x1U, I40E_PFPCI_CLASS_RESERVED_1_SHIFT)
sys/dev/pci/if_ixlreg.h
1977
#define I40E_PFPCI_CLASS_PF_IS_LAN_MASK I40E_MASK(0x1U, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT)
sys/dev/pci/if_ixlreg.h
1980
#define I40E_PFPCI_CNF_MSI_EN_MASK I40E_MASK(0x1U, I40E_PFPCI_CNF_MSI_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1982
#define I40E_PFPCI_CNF_EXROM_DIS_MASK I40E_MASK(0x1U, I40E_PFPCI_CNF_EXROM_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
1984
#define I40E_PFPCI_CNF_IO_BAR_MASK I40E_MASK(0x1U, I40E_PFPCI_CNF_IO_BAR_SHIFT)
sys/dev/pci/if_ixlreg.h
1986
#define I40E_PFPCI_CNF_INT_PIN_MASK I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT)
sys/dev/pci/if_ixlreg.h
1989
#define I40E_PFPCI_DEVID_PF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
199
#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1U, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
1991
#define I40E_PFPCI_DEVID_VF_DEV_ID_MASK I40E_MASK(0xFFFFU, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
1994
#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)
sys/dev/pci/if_ixlreg.h
1996
#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK I40E_MASK(0x1U, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
1999
#define I40E_PFPCI_FUNC_FUNC_DIS_MASK I40E_MASK(0x1U, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
2001
#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK I40E_MASK(0x1U, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
2003
#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK I40E_MASK(0x1U, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
2006
#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK I40E_MASK(0x1U, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
2009
#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT)
sys/dev/pci/if_ixlreg.h
2012
#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
2015
#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1U, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
2018
#define I40E_PFPCI_PM_PME_EN_MASK I40E_MASK(0x1U, I40E_PFPCI_PM_PME_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
2021
#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK I40E_MASK(0x1U, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
2024
#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
2026
#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK I40E_MASK(0xFFFFU, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
2029
#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1U, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
203
#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)
sys/dev/pci/if_ixlreg.h
2033
#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK I40E_MASK(0x1U, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
2036
#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1U, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
2039
#define I40E_PFPCI_VMINDEX_VMINDEX_MASK I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT)
sys/dev/pci/if_ixlreg.h
2042
#define I40E_PFPCI_VMPEND_PENDING_MASK I40E_MASK(0x1U, I40E_PFPCI_VMPEND_PENDING_SHIFT)
sys/dev/pci/if_ixlreg.h
2045
#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK I40E_MASK(0x1U, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)
sys/dev/pci/if_ixlreg.h
2047
#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1U, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)
sys/dev/pci/if_ixlreg.h
2049
#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1U, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)
sys/dev/pci/if_ixlreg.h
2052
#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT)
sys/dev/pci/if_ixlreg.h
2054
#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT)
sys/dev/pci/if_ixlreg.h
2056
#define I40E_PRTPM_EEEC_TEEE_DLY_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT)
sys/dev/pci/if_ixlreg.h
2059
#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK I40E_MASK(0x1U, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
206
#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
2062
#define I40E_PRTPM_EEER_TW_SYSTEM_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT)
sys/dev/pci/if_ixlreg.h
2064
#define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1U, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
2067
#define I40E_PRTPM_EEETXC_TW_PHY_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT)
sys/dev/pci/if_ixlreg.h
2070
#define I40E_PRTPM_GC_EMP_LINK_ON_MASK I40E_MASK(0x1U, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT)
sys/dev/pci/if_ixlreg.h
2072
#define I40E_PRTPM_GC_MNG_VETO_MASK I40E_MASK(0x1U, I40E_PRTPM_GC_MNG_VETO_SHIFT)
sys/dev/pci/if_ixlreg.h
2074
#define I40E_PRTPM_GC_RATD_MASK I40E_MASK(0x1U, I40E_PRTPM_GC_RATD_SHIFT)
sys/dev/pci/if_ixlreg.h
2076
#define I40E_PRTPM_GC_LCDMP_MASK I40E_MASK(0x1U, I40E_PRTPM_GC_LCDMP_SHIFT)
sys/dev/pci/if_ixlreg.h
2078
#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1U, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
sys/dev/pci/if_ixlreg.h
2081
#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
sys/dev/pci/if_ixlreg.h
2084
#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
sys/dev/pci/if_ixlreg.h
2087
#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
sys/dev/pci/if_ixlreg.h
209
#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
2090
#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)
sys/dev/pci/if_ixlreg.h
2093
#define I40E_GLRPB_GLW_GLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT)
sys/dev/pci/if_ixlreg.h
2096
#define I40E_GLRPB_PHW_PHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT)
sys/dev/pci/if_ixlreg.h
2099
#define I40E_GLRPB_PLW_PLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT)
sys/dev/pci/if_ixlreg.h
2103
#define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT)
sys/dev/pci/if_ixlreg.h
2107
#define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT)
sys/dev/pci/if_ixlreg.h
211
#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
2111
#define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT)
sys/dev/pci/if_ixlreg.h
2115
#define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT)
sys/dev/pci/if_ixlreg.h
2118
#define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT)
sys/dev/pci/if_ixlreg.h
2122
#define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT)
sys/dev/pci/if_ixlreg.h
2125
#define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT)
sys/dev/pci/if_ixlreg.h
2128
#define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT)
sys/dev/pci/if_ixlreg.h
213
#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
2131
#define I40E_GLQF_CTL_HTOEP_MASK I40E_MASK(0x1U, I40E_GLQF_CTL_HTOEP_SHIFT)
sys/dev/pci/if_ixlreg.h
2133
#define I40E_GLQF_CTL_HTOEP_FCOE_MASK I40E_MASK(0x1U, I40E_GLQF_CTL_HTOEP_FCOE_SHIFT)
sys/dev/pci/if_ixlreg.h
2135
#define I40E_GLQF_CTL_PCNT_ALLOC_MASK I40E_MASK(0x7, I40E_GLQF_CTL_PCNT_ALLOC_SHIFT)
sys/dev/pci/if_ixlreg.h
2137
#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK I40E_MASK(0x1U, I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
2139
#define I40E_GLQF_CTL_RSVD_MASK I40E_MASK(0x1U, I40E_GLQF_CTL_RSVD_SHIFT)
sys/dev/pci/if_ixlreg.h
2141
#define I40E_GLQF_CTL_MAXPEBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXPEBLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
2143
#define I40E_GLQF_CTL_MAXFCBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFCBLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
2145
#define I40E_GLQF_CTL_MAXFDBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFDBLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
2147
#define I40E_GLQF_CTL_FDBEST_MASK I40E_MASK(0xFF, I40E_GLQF_CTL_FDBEST_SHIFT)
sys/dev/pci/if_ixlreg.h
2149
#define I40E_GLQF_CTL_PROGPRIO_MASK I40E_MASK(0x1U, I40E_GLQF_CTL_PROGPRIO_SHIFT)
sys/dev/pci/if_ixlreg.h
2151
#define I40E_GLQF_CTL_INVALPRIO_MASK I40E_MASK(0x1U, I40E_GLQF_CTL_INVALPRIO_SHIFT)
sys/dev/pci/if_ixlreg.h
2153
#define I40E_GLQF_CTL_IGNORE_IP_MASK I40E_MASK(0x1U, I40E_GLQF_CTL_IGNORE_IP_SHIFT)
sys/dev/pci/if_ixlreg.h
2156
#define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2158
#define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
216
#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1U, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
2162
#define I40E_GLQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT)
sys/dev/pci/if_ixlreg.h
2164
#define I40E_GLQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_1_SHIFT)
sys/dev/pci/if_ixlreg.h
2166
#define I40E_GLQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT)
sys/dev/pci/if_ixlreg.h
2168
#define I40E_GLQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT)
sys/dev/pci/if_ixlreg.h
2172
#define I40E_GLQF_HSYM_SYMH_ENA_MASK I40E_MASK(0x1U, I40E_GLQF_HSYM_SYMH_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2176
#define I40E_GLQF_PCNT_PCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
218
#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT)
sys/dev/pci/if_ixlreg.h
2180
#define I40E_GLQF_SWAP_OFF0_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT)
sys/dev/pci/if_ixlreg.h
2182
#define I40E_GLQF_SWAP_OFF0_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC1_SHIFT)
sys/dev/pci/if_ixlreg.h
2184
#define I40E_GLQF_SWAP_FLEN0_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN0_SHIFT)
sys/dev/pci/if_ixlreg.h
2186
#define I40E_GLQF_SWAP_OFF1_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC0_SHIFT)
sys/dev/pci/if_ixlreg.h
2188
#define I40E_GLQF_SWAP_OFF1_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT)
sys/dev/pci/if_ixlreg.h
2190
#define I40E_GLQF_SWAP_FLEN1_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT)
sys/dev/pci/if_ixlreg.h
2193
#define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2195
#define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2197
#define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2199
#define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
220
#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2201
#define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1U, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2203
#define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1U, I40E_PFQF_CTL_0_FD_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2205
#define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1U, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2207
#define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1U, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2209
#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2211
#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2214
#define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1U, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
2217
#define I40E_PFQF_FDALLOC_FDALLOC_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT)
sys/dev/pci/if_ixlreg.h
2219
#define I40E_PFQF_FDALLOC_FDBEST_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT)
sys/dev/pci/if_ixlreg.h
222
#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2222
#define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2224
#define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2228
#define I40E_PFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2232
#define I40E_PFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_0_SHIFT)
sys/dev/pci/if_ixlreg.h
2234
#define I40E_PFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_1_SHIFT)
sys/dev/pci/if_ixlreg.h
2236
#define I40E_PFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_2_SHIFT)
sys/dev/pci/if_ixlreg.h
2238
#define I40E_PFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_3_SHIFT)
sys/dev/pci/if_ixlreg.h
224
#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2242
#define I40E_PFQF_HLUT_LUT0_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT0_SHIFT)
sys/dev/pci/if_ixlreg.h
2244
#define I40E_PFQF_HLUT_LUT1_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT1_SHIFT)
sys/dev/pci/if_ixlreg.h
2246
#define I40E_PFQF_HLUT_LUT2_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT2_SHIFT)
sys/dev/pci/if_ixlreg.h
2248
#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT)
sys/dev/pci/if_ixlreg.h
2251
#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1U, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2255
#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)
sys/dev/pci/if_ixlreg.h
2259
#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
2261
#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT)
sys/dev/pci/if_ixlreg.h
2265
#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
sys/dev/pci/if_ixlreg.h
2267
#define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2269
#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
sys/dev/pci/if_ixlreg.h
227
#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
2273
#define I40E_VFQF_HENA1_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA1_PTYPE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2277
#define I40E_VFQF_HKEY1_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_0_SHIFT)
sys/dev/pci/if_ixlreg.h
2279
#define I40E_VFQF_HKEY1_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_1_SHIFT)
sys/dev/pci/if_ixlreg.h
2281
#define I40E_VFQF_HKEY1_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_2_SHIFT)
sys/dev/pci/if_ixlreg.h
2283
#define I40E_VFQF_HKEY1_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_3_SHIFT)
sys/dev/pci/if_ixlreg.h
2287
#define I40E_VFQF_HLUT1_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT0_SHIFT)
sys/dev/pci/if_ixlreg.h
2289
#define I40E_VFQF_HLUT1_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT1_SHIFT)
sys/dev/pci/if_ixlreg.h
229
#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK I40E_MASK(0x7, I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT)
sys/dev/pci/if_ixlreg.h
2291
#define I40E_VFQF_HLUT1_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT2_SHIFT)
sys/dev/pci/if_ixlreg.h
2293
#define I40E_VFQF_HLUT1_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT3_SHIFT)
sys/dev/pci/if_ixlreg.h
2297
#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT)
sys/dev/pci/if_ixlreg.h
2299
#define I40E_VFQF_HREGION1_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_0_SHIFT)
sys/dev/pci/if_ixlreg.h
2301
#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT)
sys/dev/pci/if_ixlreg.h
2303
#define I40E_VFQF_HREGION1_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_1_SHIFT)
sys/dev/pci/if_ixlreg.h
2305
#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT)
sys/dev/pci/if_ixlreg.h
2307
#define I40E_VFQF_HREGION1_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_2_SHIFT)
sys/dev/pci/if_ixlreg.h
2309
#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT)
sys/dev/pci/if_ixlreg.h
231
#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
2311
#define I40E_VFQF_HREGION1_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_3_SHIFT)
sys/dev/pci/if_ixlreg.h
2313
#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT)
sys/dev/pci/if_ixlreg.h
2315
#define I40E_VFQF_HREGION1_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_4_SHIFT)
sys/dev/pci/if_ixlreg.h
2317
#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT)
sys/dev/pci/if_ixlreg.h
2319
#define I40E_VFQF_HREGION1_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_5_SHIFT)
sys/dev/pci/if_ixlreg.h
2321
#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT)
sys/dev/pci/if_ixlreg.h
2323
#define I40E_VFQF_HREGION1_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_6_SHIFT)
sys/dev/pci/if_ixlreg.h
2325
#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT)
sys/dev/pci/if_ixlreg.h
2327
#define I40E_VFQF_HREGION1_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_7_SHIFT)
sys/dev/pci/if_ixlreg.h
233
#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
2331
#define I40E_VPQF_CTL_PEHSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEHSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2333
#define I40E_VPQF_CTL_PEDSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2335
#define I40E_VPQF_CTL_FCHSIZE_MASK I40E_MASK(0xF, I40E_VPQF_CTL_FCHSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2337
#define I40E_VPQF_CTL_FCDSIZE_MASK I40E_MASK(0x3, I40E_VPQF_CTL_FCDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2341
#define I40E_VSIQF_CTL_FCOE_ENA_MASK I40E_MASK(0x1U, I40E_VSIQF_CTL_FCOE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2343
#define I40E_VSIQF_CTL_PETCP_ENA_MASK I40E_MASK(0x1U, I40E_VSIQF_CTL_PETCP_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2345
#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK I40E_MASK(0x1U, I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2347
#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK I40E_MASK(0x1U, I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2349
#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK I40E_MASK(0x1U, I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2351
#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK I40E_MASK(0x1U, I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2355
#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT)
sys/dev/pci/if_ixlreg.h
2357
#define I40E_VSIQF_TCREGION_TC_SIZE_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
2359
#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT)
sys/dev/pci/if_ixlreg.h
2361
#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT)
sys/dev/pci/if_ixlreg.h
2365
#define I40E_GL_FCOECRC_FCOECRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOECRC_FCOECRC_SHIFT)
sys/dev/pci/if_ixlreg.h
2369
#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT)
sys/dev/pci/if_ixlreg.h
237
#define I40E_PFCM_LANCTXDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT)
sys/dev/pci/if_ixlreg.h
2373
#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT)
sys/dev/pci/if_ixlreg.h
2377
#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT)
sys/dev/pci/if_ixlreg.h
2381
#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT)
sys/dev/pci/if_ixlreg.h
2385
#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT)
sys/dev/pci/if_ixlreg.h
2389
#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2393
#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2397
#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
240
#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK I40E_MASK(0x1U, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
2401
#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2405
#define I40E_GL_FCOELAST_FCOELAST_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOELAST_FCOELAST_SHIFT)
sys/dev/pci/if_ixlreg.h
2409
#define I40E_GL_FCOEPRC_FCOEPRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPRC_FCOEPRC_SHIFT)
sys/dev/pci/if_ixlreg.h
2413
#define I40E_GL_FCOEPTC_FCOEPTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPTC_FCOEPTC_SHIFT)
sys/dev/pci/if_ixlreg.h
2417
#define I40E_GL_FCOERPDC_FCOERPDC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOERPDC_FCOERPDC_SHIFT)
sys/dev/pci/if_ixlreg.h
242
#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK I40E_MASK(0x1U, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT)
sys/dev/pci/if_ixlreg.h
2421
#define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT)
sys/dev/pci/if_ixlreg.h
2425
#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)
sys/dev/pci/if_ixlreg.h
2429
#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2433
#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2437
#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2441
#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2445
#define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT)
sys/dev/pci/if_ixlreg.h
2449
#define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2453
#define I40E_GLPRT_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GORCL_GORCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2457
#define I40E_GLPRT_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GOTCH_GOTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
246
#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
2461
#define I40E_GLPRT_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GOTCL_GOTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2465
#define I40E_GLPRT_ILLERRC_ILLERRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ILLERRC_ILLERRC_SHIFT)
sys/dev/pci/if_ixlreg.h
2469
#define I40E_GLPRT_LDPC_LDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LDPC_LDPC_SHIFT)
sys/dev/pci/if_ixlreg.h
2473
#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2477
#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT)
sys/dev/pci/if_ixlreg.h
248
#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
2481
#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2485
#define I40E_GLPRT_LXONTXC_LXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONTXC_LXONTXC_SHIFT)
sys/dev/pci/if_ixlreg.h
2489
#define I40E_GLPRT_MLFC_MLFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MLFC_MLFC_SHIFT)
sys/dev/pci/if_ixlreg.h
2493
#define I40E_GLPRT_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPRCH_MPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2497
#define I40E_GLPRT_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPRCL_MPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
250
#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
2501
#define I40E_GLPRT_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPTCH_MPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2505
#define I40E_GLPRT_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPTCL_MPTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2509
#define I40E_GLPRT_MRFC_MRFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MRFC_MRFC_SHIFT)
sys/dev/pci/if_ixlreg.h
2513
#define I40E_GLPRT_PRC1023H_PRC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1023H_PRC1023H_SHIFT)
sys/dev/pci/if_ixlreg.h
2517
#define I40E_GLPRT_PRC1023L_PRC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1023L_PRC1023L_SHIFT)
sys/dev/pci/if_ixlreg.h
2521
#define I40E_GLPRT_PRC127H_PRC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC127H_PRC127H_SHIFT)
sys/dev/pci/if_ixlreg.h
2525
#define I40E_GLPRT_PRC127L_PRC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC127L_PRC127L_SHIFT)
sys/dev/pci/if_ixlreg.h
2529
#define I40E_GLPRT_PRC1522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1522H_PRC1522H_SHIFT)
sys/dev/pci/if_ixlreg.h
2533
#define I40E_GLPRT_PRC1522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1522L_PRC1522L_SHIFT)
sys/dev/pci/if_ixlreg.h
2537
#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT)
sys/dev/pci/if_ixlreg.h
254
#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK I40E_MASK(0x1U, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
2541
#define I40E_GLPRT_PRC255L_PRC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC255L_PRC255L_SHIFT)
sys/dev/pci/if_ixlreg.h
2545
#define I40E_GLPRT_PRC511H_PRC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC511H_PRC511H_SHIFT)
sys/dev/pci/if_ixlreg.h
2549
#define I40E_GLPRT_PRC511L_PRC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC511L_PRC511L_SHIFT)
sys/dev/pci/if_ixlreg.h
2553
#define I40E_GLPRT_PRC64H_PRC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC64H_PRC64H_SHIFT)
sys/dev/pci/if_ixlreg.h
2557
#define I40E_GLPRT_PRC64L_PRC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC64L_PRC64L_SHIFT)
sys/dev/pci/if_ixlreg.h
256
#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT)
sys/dev/pci/if_ixlreg.h
2561
#define I40E_GLPRT_PRC9522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC9522H_PRC1522H_SHIFT)
sys/dev/pci/if_ixlreg.h
2565
#define I40E_GLPRT_PRC9522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC9522L_PRC1522L_SHIFT)
sys/dev/pci/if_ixlreg.h
2569
#define I40E_GLPRT_PTC1023H_PTC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1023H_PTC1023H_SHIFT)
sys/dev/pci/if_ixlreg.h
2573
#define I40E_GLPRT_PTC1023L_PTC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1023L_PTC1023L_SHIFT)
sys/dev/pci/if_ixlreg.h
2577
#define I40E_GLPRT_PTC127H_PTC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC127H_PTC127H_SHIFT)
sys/dev/pci/if_ixlreg.h
258
#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2581
#define I40E_GLPRT_PTC127L_PTC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC127L_PTC127L_SHIFT)
sys/dev/pci/if_ixlreg.h
2585
#define I40E_GLPRT_PTC1522H_PTC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1522H_PTC1522H_SHIFT)
sys/dev/pci/if_ixlreg.h
2589
#define I40E_GLPRT_PTC1522L_PTC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1522L_PTC1522L_SHIFT)
sys/dev/pci/if_ixlreg.h
2593
#define I40E_GLPRT_PTC255H_PTC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC255H_PTC255H_SHIFT)
sys/dev/pci/if_ixlreg.h
2597
#define I40E_GLPRT_PTC255L_PTC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC255L_PTC255L_SHIFT)
sys/dev/pci/if_ixlreg.h
260
#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2601
#define I40E_GLPRT_PTC511H_PTC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC511H_PTC511H_SHIFT)
sys/dev/pci/if_ixlreg.h
2605
#define I40E_GLPRT_PTC511L_PTC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC511L_PTC511L_SHIFT)
sys/dev/pci/if_ixlreg.h
2609
#define I40E_GLPRT_PTC64H_PTC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC64H_PTC64H_SHIFT)
sys/dev/pci/if_ixlreg.h
2613
#define I40E_GLPRT_PTC64L_PTC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC64L_PTC64L_SHIFT)
sys/dev/pci/if_ixlreg.h
2617
#define I40E_GLPRT_PTC9522H_PTC9522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC9522H_PTC9522H_SHIFT)
sys/dev/pci/if_ixlreg.h
262
#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2621
#define I40E_GLPRT_PTC9522L_PTC9522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC9522L_PTC9522L_SHIFT)
sys/dev/pci/if_ixlreg.h
2625
#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2629
#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2633
#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2637
#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT)
sys/dev/pci/if_ixlreg.h
2641
#define I40E_GLPRT_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RDPC_RDPC_SHIFT)
sys/dev/pci/if_ixlreg.h
2645
#define I40E_GLPRT_RFC_RFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RFC_RFC_SHIFT)
sys/dev/pci/if_ixlreg.h
2649
#define I40E_GLPRT_RJC_RJC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RJC_RJC_SHIFT)
sys/dev/pci/if_ixlreg.h
265
#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)
sys/dev/pci/if_ixlreg.h
2653
#define I40E_GLPRT_RLEC_RLEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RLEC_RLEC_SHIFT)
sys/dev/pci/if_ixlreg.h
2657
#define I40E_GLPRT_ROC_ROC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ROC_ROC_SHIFT)
sys/dev/pci/if_ixlreg.h
2661
#define I40E_GLPRT_RUC_RUC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUC_RUC_SHIFT)
sys/dev/pci/if_ixlreg.h
2665
#define I40E_GLPRT_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUPP_RUPP_SHIFT)
sys/dev/pci/if_ixlreg.h
2669
#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2673
#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
sys/dev/pci/if_ixlreg.h
2677
#define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
268
#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT)
sys/dev/pci/if_ixlreg.h
2681
#define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2685
#define I40E_GLPRT_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPTCH_UPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2689
#define I40E_GLPRT_UPTCL_VUPTCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPTCL_VUPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2693
#define I40E_GLSW_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPRCH_BPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2697
#define I40E_GLSW_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPRCL_BPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2701
#define I40E_GLSW_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPTCH_BPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2705
#define I40E_GLSW_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPTCL_BPTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2709
#define I40E_GLSW_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GORCH_GORCH_SHIFT)
sys/dev/pci/if_ixlreg.h
271
#define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)
sys/dev/pci/if_ixlreg.h
2713
#define I40E_GLSW_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GORCL_GORCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2717
#define I40E_GLSW_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GOTCH_GOTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2721
#define I40E_GLSW_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GOTCL_GOTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2725
#define I40E_GLSW_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPRCH_MPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2729
#define I40E_GLSW_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPRCL_MPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2733
#define I40E_GLSW_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPTCH_MPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2737
#define I40E_GLSW_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPTCL_MPTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
274
#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT)
sys/dev/pci/if_ixlreg.h
2741
#define I40E_GLSW_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_RUPP_RUPP_SHIFT)
sys/dev/pci/if_ixlreg.h
2745
#define I40E_GLSW_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_TDPC_TDPC_SHIFT)
sys/dev/pci/if_ixlreg.h
2749
#define I40E_GLSW_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPRCH_UPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2753
#define I40E_GLSW_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPRCL_UPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2757
#define I40E_GLSW_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPTCH_UPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2761
#define I40E_GLSW_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPTCL_UPTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2765
#define I40E_GLV_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPRCH_BPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2769
#define I40E_GLV_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPRCL_BPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2773
#define I40E_GLV_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPTCH_BPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2777
#define I40E_GLV_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPTCL_BPTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
278
#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)
sys/dev/pci/if_ixlreg.h
2781
#define I40E_GLV_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GORCH_GORCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2785
#define I40E_GLV_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GORCL_GORCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2789
#define I40E_GLV_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GOTCH_GOTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2793
#define I40E_GLV_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GOTCL_GOTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2797
#define I40E_GLV_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPRCH_MPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
280
#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK I40E_MASK(0xFFFFU, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
sys/dev/pci/if_ixlreg.h
2801
#define I40E_GLV_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPRCL_MPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2805
#define I40E_GLV_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPTCH_MPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2809
#define I40E_GLV_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPTCL_MPTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2813
#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT)
sys/dev/pci/if_ixlreg.h
2817
#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT)
sys/dev/pci/if_ixlreg.h
2821
#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT)
sys/dev/pci/if_ixlreg.h
2825
#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2829
#define I40E_GLV_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPRCL_UPRCL_SHIFT)
sys/dev/pci/if_ixlreg.h
283
#define I40E_PRTDCB_GENC_RESERVED_1_MASK I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
sys/dev/pci/if_ixlreg.h
2833
#define I40E_GLV_UPTCH_GLVUPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPTCH_GLVUPTCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2837
#define I40E_GLV_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPTCL_UPTCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2841
#define I40E_GLVEBTC_RBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RBCH_TCBCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2845
#define I40E_GLVEBTC_RBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RBCL_TCBCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2849
#define I40E_GLVEBTC_RPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RPCH_TCPCH_SHIFT)
sys/dev/pci/if_ixlreg.h
285
#define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT)
sys/dev/pci/if_ixlreg.h
2853
#define I40E_GLVEBTC_RPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RPCL_TCPCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2857
#define I40E_GLVEBTC_TBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TBCH_TCBCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2861
#define I40E_GLVEBTC_TBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TBCL_TCBCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2865
#define I40E_GLVEBTC_TPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TPCH_TCPCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2869
#define I40E_GLVEBTC_TPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TPCL_TCPCL_SHIFT)
sys/dev/pci/if_ixlreg.h
287
#define I40E_PRTDCB_GENC_FCOEUP_MASK I40E_MASK(0x7, I40E_PRTDCB_GENC_FCOEUP_SHIFT)
sys/dev/pci/if_ixlreg.h
2873
#define I40E_GLVEBVL_BPCH_VLBPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_BPCH_VLBPCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2877
#define I40E_GLVEBVL_BPCL_VLBPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_BPCL_VLBPCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2881
#define I40E_GLVEBVL_GORCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GORCH_VLBCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2885
#define I40E_GLVEBVL_GORCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GORCL_VLBCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2889
#define I40E_GLVEBVL_GOTCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GOTCH_VLBCH_SHIFT)
sys/dev/pci/if_ixlreg.h
289
#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK I40E_MASK(0x1U, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
2893
#define I40E_GLVEBVL_GOTCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GOTCL_VLBCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2897
#define I40E_GLVEBVL_MPCH_VLMPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_MPCH_VLMPCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2901
#define I40E_GLVEBVL_MPCL_VLMPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_MPCL_VLMPCL_SHIFT)
sys/dev/pci/if_ixlreg.h
2905
#define I40E_GLVEBVL_UPCH_VLUPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_UPCH_VLUPCH_SHIFT)
sys/dev/pci/if_ixlreg.h
2909
#define I40E_GLVEBVL_UPCL_VLUPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_UPCL_VLUPCL_SHIFT)
sys/dev/pci/if_ixlreg.h
291
#define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFFU, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
sys/dev/pci/if_ixlreg.h
2912
#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK I40E_MASK(0xFFFF, I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT)
sys/dev/pci/if_ixlreg.h
2916
#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT)
sys/dev/pci/if_ixlreg.h
2920
#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT)
sys/dev/pci/if_ixlreg.h
2923
#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK I40E_MASK(0x7FFFFFFF, I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT)
sys/dev/pci/if_ixlreg.h
2925
#define I40E_PRTTSYN_ADJ_SIGN_MASK I40E_MASK(0x1U, I40E_PRTTSYN_ADJ_SIGN_SHIFT)
sys/dev/pci/if_ixlreg.h
2929
#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK I40E_MASK(0x1U, I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2931
#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
sys/dev/pci/if_ixlreg.h
2933
#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK I40E_MASK(0x1U, I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT)
sys/dev/pci/if_ixlreg.h
2935
#define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
sys/dev/pci/if_ixlreg.h
2937
#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
sys/dev/pci/if_ixlreg.h
294
#define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
sys/dev/pci/if_ixlreg.h
2941
#define I40E_PRTTSYN_AUX_1_INSTNT_MASK I40E_MASK(0x1U, I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
sys/dev/pci/if_ixlreg.h
2943
#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK I40E_MASK(0x1U, I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT)
sys/dev/pci/if_ixlreg.h
2947
#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT)
sys/dev/pci/if_ixlreg.h
2950
#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK I40E_MASK(0x1U, I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT)
sys/dev/pci/if_ixlreg.h
2952
#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1U, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2954
#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1U, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2956
#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK I40E_MASK(0x1U, I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2958
#define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
2960
#define I40E_PRTTSYN_CTL0_TSYNACT_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL0_TSYNACT_SHIFT)
sys/dev/pci/if_ixlreg.h
2962
#define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1U, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2965
#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT)
sys/dev/pci/if_ixlreg.h
2967
#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT)
sys/dev/pci/if_ixlreg.h
2969
#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT)
sys/dev/pci/if_ixlreg.h
297
#define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1U, I40E_PRTDCB_MFLCN_PMCF_SHIFT)
sys/dev/pci/if_ixlreg.h
2971
#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT)
sys/dev/pci/if_ixlreg.h
2973
#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
2975
#define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2977
#define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1U, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)
sys/dev/pci/if_ixlreg.h
2981
#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT)
sys/dev/pci/if_ixlreg.h
2985
#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT)
sys/dev/pci/if_ixlreg.h
2988
#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK I40E_MASK(0x3F, I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT)
sys/dev/pci/if_ixlreg.h
299
#define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1U, I40E_PRTDCB_MFLCN_DPF_SHIFT)
sys/dev/pci/if_ixlreg.h
2991
#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT)
sys/dev/pci/if_ixlreg.h
2995
#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT)
sys/dev/pci/if_ixlreg.h
2999
#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT)
sys/dev/pci/if_ixlreg.h
3002
#define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)
sys/dev/pci/if_ixlreg.h
3004
#define I40E_PRTTSYN_STAT_0_EVENT1_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_0_EVENT1_SHIFT)
sys/dev/pci/if_ixlreg.h
3006
#define I40E_PRTTSYN_STAT_0_TGT0_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_0_TGT0_SHIFT)
sys/dev/pci/if_ixlreg.h
3008
#define I40E_PRTTSYN_STAT_0_TGT1_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_0_TGT1_SHIFT)
sys/dev/pci/if_ixlreg.h
301
#define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1U, I40E_PRTDCB_MFLCN_RPFCM_SHIFT)
sys/dev/pci/if_ixlreg.h
3010
#define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)
sys/dev/pci/if_ixlreg.h
3013
#define I40E_PRTTSYN_STAT_1_RXT0_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_1_RXT0_SHIFT)
sys/dev/pci/if_ixlreg.h
3015
#define I40E_PRTTSYN_STAT_1_RXT1_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_1_RXT1_SHIFT)
sys/dev/pci/if_ixlreg.h
3017
#define I40E_PRTTSYN_STAT_1_RXT2_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_1_RXT2_SHIFT)
sys/dev/pci/if_ixlreg.h
3019
#define I40E_PRTTSYN_STAT_1_RXT3_MASK I40E_MASK(0x1U, I40E_PRTTSYN_STAT_1_RXT3_SHIFT)
sys/dev/pci/if_ixlreg.h
3023
#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT)
sys/dev/pci/if_ixlreg.h
3027
#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT)
sys/dev/pci/if_ixlreg.h
303
#define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1U, I40E_PRTDCB_MFLCN_RFCE_SHIFT)
sys/dev/pci/if_ixlreg.h
3030
#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT)
sys/dev/pci/if_ixlreg.h
3033
#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT)
sys/dev/pci/if_ixlreg.h
3036
#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT)
sys/dev/pci/if_ixlreg.h
3039
#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
sys/dev/pci/if_ixlreg.h
3042
#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)
sys/dev/pci/if_ixlreg.h
3044
#define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
3046
#define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT)
sys/dev/pci/if_ixlreg.h
3048
#define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1U, I40E_GL_MDET_RX_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
305
#define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT)
sys/dev/pci/if_ixlreg.h
3051
#define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT)
sys/dev/pci/if_ixlreg.h
3053
#define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
3055
#define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
3057
#define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
3059
#define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1U, I40E_GL_MDET_TX_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
3062
#define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1U, I40E_PF_MDET_RX_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
3065
#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1U, I40E_PF_MDET_TX_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
3068
#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)
sys/dev/pci/if_ixlreg.h
3070
#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
sys/dev/pci/if_ixlreg.h
3072
#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1U, I40E_PF_VT_PFALLOC_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
3076
#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1U, I40E_VP_MDET_RX_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
308
#define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1U, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3080
#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1U, I40E_VP_MDET_TX_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
3083
#define I40E_GLPM_WUMC_NOTCO_MASK I40E_MASK(0x1U, I40E_GLPM_WUMC_NOTCO_SHIFT)
sys/dev/pci/if_ixlreg.h
3085
#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK I40E_MASK(0x1U, I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT)
sys/dev/pci/if_ixlreg.h
3087
#define I40E_GLPM_WUMC_ROL_MODE_MASK I40E_MASK(0x1U, I40E_GLPM_WUMC_ROL_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3089
#define I40E_GLPM_WUMC_RESERVED_4_MASK I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT)
sys/dev/pci/if_ixlreg.h
3091
#define I40E_GLPM_WUMC_MNG_WU_PF_MASK I40E_MASK(0xFFFFU, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
sys/dev/pci/if_ixlreg.h
3094
#define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1U, I40E_PFPM_APM_APME_SHIFT)
sys/dev/pci/if_ixlreg.h
3098
#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)
sys/dev/pci/if_ixlreg.h
310
#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1U, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3101
#define I40E_PFPM_WUC_EN_APM_D0_MASK I40E_MASK(0x1U, I40E_PFPM_WUC_EN_APM_D0_SHIFT)
sys/dev/pci/if_ixlreg.h
3104
#define I40E_PFPM_WUFC_LNKC_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_LNKC_SHIFT)
sys/dev/pci/if_ixlreg.h
3106
#define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_MAG_SHIFT)
sys/dev/pci/if_ixlreg.h
3108
#define I40E_PFPM_WUFC_MNG_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_MNG_SHIFT)
sys/dev/pci/if_ixlreg.h
3110
#define I40E_PFPM_WUFC_FLX0_ACT_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX0_ACT_SHIFT)
sys/dev/pci/if_ixlreg.h
3112
#define I40E_PFPM_WUFC_FLX1_ACT_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX1_ACT_SHIFT)
sys/dev/pci/if_ixlreg.h
3114
#define I40E_PFPM_WUFC_FLX2_ACT_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX2_ACT_SHIFT)
sys/dev/pci/if_ixlreg.h
3116
#define I40E_PFPM_WUFC_FLX3_ACT_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX3_ACT_SHIFT)
sys/dev/pci/if_ixlreg.h
3118
#define I40E_PFPM_WUFC_FLX4_ACT_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX4_ACT_SHIFT)
sys/dev/pci/if_ixlreg.h
312
#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)
sys/dev/pci/if_ixlreg.h
3120
#define I40E_PFPM_WUFC_FLX5_ACT_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX5_ACT_SHIFT)
sys/dev/pci/if_ixlreg.h
3122
#define I40E_PFPM_WUFC_FLX6_ACT_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX6_ACT_SHIFT)
sys/dev/pci/if_ixlreg.h
3124
#define I40E_PFPM_WUFC_FLX7_ACT_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX7_ACT_SHIFT)
sys/dev/pci/if_ixlreg.h
3126
#define I40E_PFPM_WUFC_FLX0_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX0_SHIFT)
sys/dev/pci/if_ixlreg.h
3128
#define I40E_PFPM_WUFC_FLX1_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX1_SHIFT)
sys/dev/pci/if_ixlreg.h
3130
#define I40E_PFPM_WUFC_FLX2_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX2_SHIFT)
sys/dev/pci/if_ixlreg.h
3132
#define I40E_PFPM_WUFC_FLX3_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX3_SHIFT)
sys/dev/pci/if_ixlreg.h
3134
#define I40E_PFPM_WUFC_FLX4_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX4_SHIFT)
sys/dev/pci/if_ixlreg.h
3136
#define I40E_PFPM_WUFC_FLX5_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX5_SHIFT)
sys/dev/pci/if_ixlreg.h
3138
#define I40E_PFPM_WUFC_FLX6_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX6_SHIFT)
sys/dev/pci/if_ixlreg.h
314
#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)
sys/dev/pci/if_ixlreg.h
3140
#define I40E_PFPM_WUFC_FLX7_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FLX7_SHIFT)
sys/dev/pci/if_ixlreg.h
3142
#define I40E_PFPM_WUFC_FW_RST_WK_MASK I40E_MASK(0x1U, I40E_PFPM_WUFC_FW_RST_WK_SHIFT)
sys/dev/pci/if_ixlreg.h
3145
#define I40E_PFPM_WUS_LNKC_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_LNKC_SHIFT)
sys/dev/pci/if_ixlreg.h
3147
#define I40E_PFPM_WUS_MAG_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_MAG_SHIFT)
sys/dev/pci/if_ixlreg.h
3149
#define I40E_PFPM_WUS_PME_STATUS_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_PME_STATUS_SHIFT)
sys/dev/pci/if_ixlreg.h
3151
#define I40E_PFPM_WUS_MNG_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_MNG_SHIFT)
sys/dev/pci/if_ixlreg.h
3153
#define I40E_PFPM_WUS_FLX0_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FLX0_SHIFT)
sys/dev/pci/if_ixlreg.h
3155
#define I40E_PFPM_WUS_FLX1_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FLX1_SHIFT)
sys/dev/pci/if_ixlreg.h
3157
#define I40E_PFPM_WUS_FLX2_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FLX2_SHIFT)
sys/dev/pci/if_ixlreg.h
3159
#define I40E_PFPM_WUS_FLX3_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FLX3_SHIFT)
sys/dev/pci/if_ixlreg.h
3161
#define I40E_PFPM_WUS_FLX4_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FLX4_SHIFT)
sys/dev/pci/if_ixlreg.h
3163
#define I40E_PFPM_WUS_FLX5_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FLX5_SHIFT)
sys/dev/pci/if_ixlreg.h
3165
#define I40E_PFPM_WUS_FLX6_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FLX6_SHIFT)
sys/dev/pci/if_ixlreg.h
3167
#define I40E_PFPM_WUS_FLX7_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FLX7_SHIFT)
sys/dev/pci/if_ixlreg.h
3169
#define I40E_PFPM_WUS_FW_RST_WK_MASK I40E_MASK(0x1U, I40E_PFPM_WUS_FW_RST_WK_SHIFT)
sys/dev/pci/if_ixlreg.h
3172
#define I40E_PRTPM_FHFHR_UNICAST_MASK I40E_MASK(0x1U, I40E_PRTPM_FHFHR_UNICAST_SHIFT)
sys/dev/pci/if_ixlreg.h
3174
#define I40E_PRTPM_FHFHR_MULTICAST_MASK I40E_MASK(0x1U, I40E_PRTPM_FHFHR_MULTICAST_SHIFT)
sys/dev/pci/if_ixlreg.h
3178
#define I40E_PRTPM_SAH_PFPM_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTPM_SAH_PFPM_SAH_SHIFT)
sys/dev/pci/if_ixlreg.h
318
#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
sys/dev/pci/if_ixlreg.h
3180
#define I40E_PRTPM_SAH_PF_NUM_MASK I40E_MASK(0xF, I40E_PRTPM_SAH_PF_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
3182
#define I40E_PRTPM_SAH_MC_MAG_EN_MASK I40E_MASK(0x1U, I40E_PRTPM_SAH_MC_MAG_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
3184
#define I40E_PRTPM_SAH_AV_MASK I40E_MASK(0x1U, I40E_PRTPM_SAH_AV_SHIFT)
sys/dev/pci/if_ixlreg.h
3188
#define I40E_PRTPM_SAL_PFPM_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT)
sys/dev/pci/if_ixlreg.h
3191
#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)
sys/dev/pci/if_ixlreg.h
3194
#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)
sys/dev/pci/if_ixlreg.h
3197
#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)
sys/dev/pci/if_ixlreg.h
320
#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1U, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3200
#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
3202
#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1U, I40E_VF_ARQLEN1_ARQVFE_SHIFT)
sys/dev/pci/if_ixlreg.h
3204
#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1U, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)
sys/dev/pci/if_ixlreg.h
3206
#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1U, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
sys/dev/pci/if_ixlreg.h
3208
#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1U, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
3211
#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
sys/dev/pci/if_ixlreg.h
3214
#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)
sys/dev/pci/if_ixlreg.h
3217
#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)
sys/dev/pci/if_ixlreg.h
322
#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1U, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
sys/dev/pci/if_ixlreg.h
3220
#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)
sys/dev/pci/if_ixlreg.h
3223
#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
3225
#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1U, I40E_VF_ATQLEN1_ATQVFE_SHIFT)
sys/dev/pci/if_ixlreg.h
3227
#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1U, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)
sys/dev/pci/if_ixlreg.h
3229
#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1U, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
sys/dev/pci/if_ixlreg.h
3231
#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1U, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
3234
#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
sys/dev/pci/if_ixlreg.h
3237
#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
sys/dev/pci/if_ixlreg.h
3240
#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)
sys/dev/pci/if_ixlreg.h
3242
#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
sys/dev/pci/if_ixlreg.h
3244
#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
sys/dev/pci/if_ixlreg.h
3246
#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
3248
#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
325
#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
sys/dev/pci/if_ixlreg.h
3250
#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
3252
#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
3254
#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)
sys/dev/pci/if_ixlreg.h
3258
#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)
sys/dev/pci/if_ixlreg.h
3260
#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
sys/dev/pci/if_ixlreg.h
3262
#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
sys/dev/pci/if_ixlreg.h
3264
#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
3266
#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
3268
#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
327
#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
sys/dev/pci/if_ixlreg.h
3270
#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
3272
#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
sys/dev/pci/if_ixlreg.h
3275
#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
3277
#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
sys/dev/pci/if_ixlreg.h
3279
#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1U, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)
sys/dev/pci/if_ixlreg.h
3282
#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1U, I40E_VFINT_ICR01_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
3284
#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1U, I40E_VFINT_ICR01_QUEUE_0_SHIFT)
sys/dev/pci/if_ixlreg.h
3286
#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1U, I40E_VFINT_ICR01_QUEUE_1_SHIFT)
sys/dev/pci/if_ixlreg.h
3288
#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1U, I40E_VFINT_ICR01_QUEUE_2_SHIFT)
sys/dev/pci/if_ixlreg.h
329
#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3290
#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1U, I40E_VFINT_ICR01_QUEUE_3_SHIFT)
sys/dev/pci/if_ixlreg.h
3292
#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1U, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
3294
#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1U, I40E_VFINT_ICR01_ADMINQ_SHIFT)
sys/dev/pci/if_ixlreg.h
3296
#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1U, I40E_VFINT_ICR01_SWINT_SHIFT)
sys/dev/pci/if_ixlreg.h
3300
#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
3304
#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
3307
#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
3311
#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
3315
#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
3318
#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)
sys/dev/pci/if_ixlreg.h
332
#define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT)
sys/dev/pci/if_ixlreg.h
3322
#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
sys/dev/pci/if_ixlreg.h
3324
#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
sys/dev/pci/if_ixlreg.h
3328
#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
sys/dev/pci/if_ixlreg.h
3332
#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
sys/dev/pci/if_ixlreg.h
3336
#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1U, I40E_VFMSIX_TVCTRL_MASK_SHIFT)
sys/dev/pci/if_ixlreg.h
3339
#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3341
#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
3343
#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
3346
#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1U, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
3348
#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)
sys/dev/pci/if_ixlreg.h
335
#define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)
sys/dev/pci/if_ixlreg.h
3350
#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3352
#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3354
#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3358
#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
3362
#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)
sys/dev/pci/if_ixlreg.h
3364
#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT)
sys/dev/pci/if_ixlreg.h
3366
#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)
sys/dev/pci/if_ixlreg.h
3368
#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)
sys/dev/pci/if_ixlreg.h
337
#define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT)
sys/dev/pci/if_ixlreg.h
3372
#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)
sys/dev/pci/if_ixlreg.h
3374
#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT)
sys/dev/pci/if_ixlreg.h
3376
#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)
sys/dev/pci/if_ixlreg.h
3378
#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)
sys/dev/pci/if_ixlreg.h
3382
#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
sys/dev/pci/if_ixlreg.h
3384
#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT)
sys/dev/pci/if_ixlreg.h
3386
#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
sys/dev/pci/if_ixlreg.h
3388
#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT)
sys/dev/pci/if_ixlreg.h
339
#define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT)
sys/dev/pci/if_ixlreg.h
3390
#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
sys/dev/pci/if_ixlreg.h
3392
#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT)
sys/dev/pci/if_ixlreg.h
3394
#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
sys/dev/pci/if_ixlreg.h
3396
#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT)
sys/dev/pci/if_ixlreg.h
3398
#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
sys/dev/pci/if_ixlreg.h
3400
#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT)
sys/dev/pci/if_ixlreg.h
3402
#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
sys/dev/pci/if_ixlreg.h
3404
#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT)
sys/dev/pci/if_ixlreg.h
3406
#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
sys/dev/pci/if_ixlreg.h
3408
#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)
sys/dev/pci/if_ixlreg.h
341
#define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT)
sys/dev/pci/if_ixlreg.h
3410
#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1U, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
sys/dev/pci/if_ixlreg.h
3412
#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)
sys/dev/pci/if_ixlreg.h
3417
#define I40E_MNGSB_FDCRC_CRC_RES_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCRC_CRC_RES_SHIFT)
sys/dev/pci/if_ixlreg.h
3420
#define I40E_MNGSB_FDCS_CRC_CONT_MASK I40E_MASK(0x1U, I40E_MNGSB_FDCS_CRC_CONT_SHIFT)
sys/dev/pci/if_ixlreg.h
3422
#define I40E_MNGSB_FDCS_CRC_SEED_EN_MASK I40E_MASK(0x1U, I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
3424
#define I40E_MNGSB_FDCS_CRC_WR_INH_MASK I40E_MASK(0x1U, I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT)
sys/dev/pci/if_ixlreg.h
3426
#define I40E_MNGSB_FDCS_CRC_SEED_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCS_CRC_SEED_SHIFT)
sys/dev/pci/if_ixlreg.h
3429
#define I40E_MNGSB_FDS_START_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_START_BC_SHIFT)
sys/dev/pci/if_ixlreg.h
343
#define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT)
sys/dev/pci/if_ixlreg.h
3431
#define I40E_MNGSB_FDS_LAST_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_LAST_BC_SHIFT)
sys/dev/pci/if_ixlreg.h
3436
#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_MASK I40E_MASK(0x1U, I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
3440
#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_MASK I40E_MASK(0x1U, I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
3444
#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3446
#define I40E_GLCM_LAN_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT)
sys/dev/pci/if_ixlreg.h
3448
#define I40E_GLCM_LAN_CACHESIZE_WAYS_MASK I40E_MASK(0x3FF, I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT)
sys/dev/pci/if_ixlreg.h
345
#define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT)
sys/dev/pci/if_ixlreg.h
3451
#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3453
#define I40E_GLCM_PE_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_PE_CACHESIZE_SETS_SHIFT)
sys/dev/pci/if_ixlreg.h
3455
#define I40E_GLCM_PE_CACHESIZE_WAYS_MASK I40E_MASK(0x1FF, I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT)
sys/dev/pci/if_ixlreg.h
3458
#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3460
#define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
3462
#define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
3465
#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1U, I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
3467
#define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT)
sys/dev/pci/if_ixlreg.h
3469
#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
347
#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
sys/dev/pci/if_ixlreg.h
3471
#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3473
#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3478
#define I40E_PRTDCB_TFMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TFMSTC_MSTC_SHIFT)
sys/dev/pci/if_ixlreg.h
3480
#define I40E_GL_FWSTS_FWROWD_MASK I40E_MASK(0x1U, I40E_GL_FWSTS_FWROWD_SHIFT)
sys/dev/pci/if_ixlreg.h
3483
#define I40E_GLFOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3485
#define I40E_GLFOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLFOC_CACHESIZE_SETS_SHIFT)
sys/dev/pci/if_ixlreg.h
3487
#define I40E_GLFOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLFOC_CACHESIZE_WAYS_SHIFT)
sys/dev/pci/if_ixlreg.h
349
#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
sys/dev/pci/if_ixlreg.h
3491
#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3495
#define I40E_GLHMC_CEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3497
#define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3500
#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_MASK I40E_MASK(0x3FFFF, I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3504
#define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3506
#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3509
#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_MASK I40E_MASK(0x7FFFF, I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3513
#define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3515
#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3519
#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3523
#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3526
#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3529
#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK I40E_MASK(0x7, I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
353
#define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)
sys/dev/pci/if_ixlreg.h
3533
#define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3537
#define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3540
#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
3544
#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3548
#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3551
#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
3554
#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK I40E_MASK(0x1FFFFF, I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3558
#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
356
#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
sys/dev/pci/if_ixlreg.h
3562
#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
3565
#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3568
#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
3572
#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3576
#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3579
#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3582
#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_MASK I40E_MASK(0xFFF, I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT)
sys/dev/pci/if_ixlreg.h
3586
#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3590
#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3594
#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3597
#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
360
#define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT)
sys/dev/pci/if_ixlreg.h
3600
#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3603
#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
3607
#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3611
#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3614
#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
3618
#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3622
#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3625
#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3628
#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
363
#define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT)
sys/dev/pci/if_ixlreg.h
3632
#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3636
#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3639
#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3642
#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
3646
#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
365
#define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT)
sys/dev/pci/if_ixlreg.h
3650
#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3654
#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3657
#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK I40E_MASK(0x1FFFFFF, I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3660
#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
3663
#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
3667
#define I40E_GLHMC_PFPESDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3669
#define I40E_GLHMC_PFPESDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
367
#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1U, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3673
#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3677
#define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3679
#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3683
#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3685
#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3689
#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3691
#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3695
#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3699
#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3703
#define I40E_GLHMC_VFPDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT)
sys/dev/pci/if_ixlreg.h
3705
#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_MASK I40E_MASK(0x1U, I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT)
sys/dev/pci/if_ixlreg.h
3707
#define I40E_GLHMC_VFPDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT)
sys/dev/pci/if_ixlreg.h
371
#define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT)
sys/dev/pci/if_ixlreg.h
3711
#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3715
#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3719
#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3723
#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3727
#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3731
#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3735
#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3739
#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
374
#define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT)
sys/dev/pci/if_ixlreg.h
3743
#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3747
#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3751
#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3755
#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3759
#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
376
#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1U, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3763
#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3767
#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3771
#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3775
#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3779
#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3783
#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3787
#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
379
#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1U, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)
sys/dev/pci/if_ixlreg.h
3791
#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
3795
#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3799
#define I40E_GLHMC_VFSDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
3801
#define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3804
#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3806
#define I40E_GLPBLOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPBLOC_CACHESIZE_SETS_SHIFT)
sys/dev/pci/if_ixlreg.h
3808
#define I40E_GLPBLOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT)
sys/dev/pci/if_ixlreg.h
381
#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)
sys/dev/pci/if_ixlreg.h
3811
#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3813
#define I40E_GLPDOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPDOC_CACHESIZE_SETS_SHIFT)
sys/dev/pci/if_ixlreg.h
3815
#define I40E_GLPDOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPDOC_CACHESIZE_WAYS_SHIFT)
sys/dev/pci/if_ixlreg.h
3818
#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
3820
#define I40E_GLPEOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPEOC_CACHESIZE_SETS_SHIFT)
sys/dev/pci/if_ixlreg.h
3822
#define I40E_GLPEOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPEOC_CACHESIZE_WAYS_SHIFT)
sys/dev/pci/if_ixlreg.h
3824
#define I40E_PFHMC_PDINV_PMSDPARTSEL_MASK I40E_MASK(0x1U, I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT)
sys/dev/pci/if_ixlreg.h
3826
#define I40E_PFHMC_SDCMD_PMSDPARTSEL_MASK I40E_MASK(0x1U, I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT)
sys/dev/pci/if_ixlreg.h
3829
#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT)
sys/dev/pci/if_ixlreg.h
3832
#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT)
sys/dev/pci/if_ixlreg.h
3835
#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT)
sys/dev/pci/if_ixlreg.h
3838
#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
384
#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1U, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)
sys/dev/pci/if_ixlreg.h
3840
#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
3842
#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
3844
#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT)
sys/dev/pci/if_ixlreg.h
3846
#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT)
sys/dev/pci/if_ixlreg.h
3848
#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT)
sys/dev/pci/if_ixlreg.h
3850
#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT)
sys/dev/pci/if_ixlreg.h
3852
#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT)
sys/dev/pci/if_ixlreg.h
3854
#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT)
sys/dev/pci/if_ixlreg.h
3856
#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT)
sys/dev/pci/if_ixlreg.h
3858
#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT)
sys/dev/pci/if_ixlreg.h
386
#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)
sys/dev/pci/if_ixlreg.h
3860
#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT)
sys/dev/pci/if_ixlreg.h
3862
#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT)
sys/dev/pci/if_ixlreg.h
3864
#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT)
sys/dev/pci/if_ixlreg.h
3866
#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_MASK I40E_MASK(0x1U, I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3869
#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT)
sys/dev/pci/if_ixlreg.h
3872
#define I40E_GL_UFUSE_SOC_PORT_MODE_MASK I40E_MASK(0x3, I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
3874
#define I40E_GL_UFUSE_SOC_NIC_ID_MASK I40E_MASK(0x1U, I40E_GL_UFUSE_SOC_NIC_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
3876
#define I40E_GL_UFUSE_SOC_SPARE_FUSES_MASK I40E_MASK(0x1FFF, I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT)
sys/dev/pci/if_ixlreg.h
3878
#define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
sys/dev/pci/if_ixlreg.h
3880
#define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
sys/dev/pci/if_ixlreg.h
3882
#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
sys/dev/pci/if_ixlreg.h
3884
#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
sys/dev/pci/if_ixlreg.h
3888
#define I40E_VPLAN_QBASE_VFFIRSTQ_MASK I40E_MASK(0x7FF, I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT)
sys/dev/pci/if_ixlreg.h
389
#define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF_SHIFT)
sys/dev/pci/if_ixlreg.h
3890
#define I40E_VPLAN_QBASE_VFNUMQ_MASK I40E_MASK(0xFF, I40E_VPLAN_QBASE_VFNUMQ_SHIFT)
sys/dev/pci/if_ixlreg.h
3892
#define I40E_VPLAN_QBASE_VFQTABLE_ENA_MASK I40E_MASK(0x1U, I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
3895
#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT)
sys/dev/pci/if_ixlreg.h
3898
#define I40E_GLNVM_AL_REQ_POR_MASK I40E_MASK(0x1U, I40E_GLNVM_AL_REQ_POR_SHIFT)
sys/dev/pci/if_ixlreg.h
3900
#define I40E_GLNVM_AL_REQ_PCIE_IMIB_MASK I40E_MASK(0x1U, I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT)
sys/dev/pci/if_ixlreg.h
3902
#define I40E_GLNVM_AL_REQ_GLOBR_MASK I40E_MASK(0x1U, I40E_GLNVM_AL_REQ_GLOBR_SHIFT)
sys/dev/pci/if_ixlreg.h
3904
#define I40E_GLNVM_AL_REQ_CORER_MASK I40E_MASK(0x1U, I40E_GLNVM_AL_REQ_CORER_SHIFT)
sys/dev/pci/if_ixlreg.h
3906
#define I40E_GLNVM_AL_REQ_PE_MASK I40E_MASK(0x1U, I40E_GLNVM_AL_REQ_PE_SHIFT)
sys/dev/pci/if_ixlreg.h
3908
#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_MASK I40E_MASK(0x1U, I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT)
sys/dev/pci/if_ixlreg.h
391
#define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF0_SHIFT)
sys/dev/pci/if_ixlreg.h
3911
#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_MASK I40E_MASK(0xFFF, I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT)
sys/dev/pci/if_ixlreg.h
3913
#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_MASK I40E_MASK(0xFFFFF, I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT)
sys/dev/pci/if_ixlreg.h
3916
#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1U, I40E_GLNVM_FLA_LOCKED_SHIFT)
sys/dev/pci/if_ixlreg.h
3920
#define I40E_GLNVM_ULD_PCIER_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_PCIER_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3922
#define I40E_GLNVM_ULD_PCIER_DONE_1_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT)
sys/dev/pci/if_ixlreg.h
3924
#define I40E_GLNVM_ULD_CORER_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_CORER_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3926
#define I40E_GLNVM_ULD_GLOBR_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_GLOBR_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3928
#define I40E_GLNVM_ULD_POR_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_POR_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
393
#define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF1_SHIFT)
sys/dev/pci/if_ixlreg.h
3930
#define I40E_GLNVM_ULD_POR_DONE_1_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_POR_DONE_1_SHIFT)
sys/dev/pci/if_ixlreg.h
3932
#define I40E_GLNVM_ULD_PCIER_DONE_2_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT)
sys/dev/pci/if_ixlreg.h
3934
#define I40E_GLNVM_ULD_PE_DONE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULD_PE_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3937
#define I40E_GLNVM_ULT_CONF_PCIR_AE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT)
sys/dev/pci/if_ixlreg.h
3939
#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT)
sys/dev/pci/if_ixlreg.h
3941
#define I40E_GLNVM_ULT_RESERVED_1_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_RESERVED_1_SHIFT)
sys/dev/pci/if_ixlreg.h
3943
#define I40E_GLNVM_ULT_CONF_CORE_AE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT)
sys/dev/pci/if_ixlreg.h
3945
#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT)
sys/dev/pci/if_ixlreg.h
3947
#define I40E_GLNVM_ULT_CONF_POR_AE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_CONF_POR_AE_SHIFT)
sys/dev/pci/if_ixlreg.h
3949
#define I40E_GLNVM_ULT_RESERVED_2_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_RESERVED_2_SHIFT)
sys/dev/pci/if_ixlreg.h
395
#define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF2_SHIFT)
sys/dev/pci/if_ixlreg.h
3951
#define I40E_GLNVM_ULT_RESERVED_3_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_RESERVED_3_SHIFT)
sys/dev/pci/if_ixlreg.h
3953
#define I40E_GLNVM_ULT_CONF_EMP_AE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT)
sys/dev/pci/if_ixlreg.h
3955
#define I40E_GLNVM_ULT_CONF_PCIALT_AE_MASK I40E_MASK(0x1U, I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT)
sys/dev/pci/if_ixlreg.h
3957
#define I40E_GLNVM_ULT_RESERVED_4_MASK I40E_MASK(0x3FFFFF, I40E_GLNVM_ULT_RESERVED_4_SHIFT)
sys/dev/pci/if_ixlreg.h
3960
#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3962
#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3964
#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3966
#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3968
#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
397
#define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF3_SHIFT)
sys/dev/pci/if_ixlreg.h
3970
#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3972
#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3974
#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3976
#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3978
#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3980
#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3982
#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3984
#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3986
#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3988
#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
399
#define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF4_SHIFT)
sys/dev/pci/if_ixlreg.h
3990
#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3992
#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_MASK I40E_MASK(0x1U, I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
3995
#define I40E_MNGSB_DADD_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DADD_ADDR_SHIFT)
sys/dev/pci/if_ixlreg.h
3998
#define I40E_MNGSB_DCNT_BYTE_CNT_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DCNT_BYTE_CNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4001
#define I40E_MNGSB_MSGCTL_HDR_DWS_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT)
sys/dev/pci/if_ixlreg.h
4003
#define I40E_MNGSB_MSGCTL_EXP_RDW_MASK I40E_MASK(0x1FF, I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT)
sys/dev/pci/if_ixlreg.h
4005
#define I40E_MNGSB_MSGCTL_MSG_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4007
#define I40E_MNGSB_MSGCTL_TOKEN_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4009
#define I40E_MNGSB_MSGCTL_BARCLR_MASK I40E_MASK(0x1U, I40E_MNGSB_MSGCTL_BARCLR_SHIFT)
sys/dev/pci/if_ixlreg.h
401
#define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF5_SHIFT)
sys/dev/pci/if_ixlreg.h
4011
#define I40E_MNGSB_MSGCTL_CMDV_MASK I40E_MASK(0x1U, I40E_MNGSB_MSGCTL_CMDV_SHIFT)
sys/dev/pci/if_ixlreg.h
4014
#define I40E_MNGSB_RDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_RDATA_DATA_SHIFT)
sys/dev/pci/if_ixlreg.h
4017
#define I40E_MNGSB_RHDR0_DESTINATION_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_DESTINATION_SHIFT)
sys/dev/pci/if_ixlreg.h
4019
#define I40E_MNGSB_RHDR0_SOURCE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_SOURCE_SHIFT)
sys/dev/pci/if_ixlreg.h
4021
#define I40E_MNGSB_RHDR0_OPCODE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_OPCODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4023
#define I40E_MNGSB_RHDR0_TAG_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_TAG_SHIFT)
sys/dev/pci/if_ixlreg.h
4025
#define I40E_MNGSB_RHDR0_RESPONSE_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_RESPONSE_SHIFT)
sys/dev/pci/if_ixlreg.h
4027
#define I40E_MNGSB_RHDR0_EH_MASK I40E_MASK(0x1U, I40E_MNGSB_RHDR0_EH_SHIFT)
sys/dev/pci/if_ixlreg.h
403
#define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF6_SHIFT)
sys/dev/pci/if_ixlreg.h
4030
#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_MASK I40E_MASK(0x1FF, I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT)
sys/dev/pci/if_ixlreg.h
4032
#define I40E_MNGSB_RSPCTL_RSP_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4034
#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_MASK I40E_MASK(0x1U, I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT)
sys/dev/pci/if_ixlreg.h
4036
#define I40E_MNGSB_RSPCTL_RSP_ERR_MASK I40E_MASK(0x1U, I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
4039
#define I40E_MNGSB_WDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WDATA_DATA_SHIFT)
sys/dev/pci/if_ixlreg.h
4042
#define I40E_MNGSB_WHDR0_RAW_DEST_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_RAW_DEST_SHIFT)
sys/dev/pci/if_ixlreg.h
4044
#define I40E_MNGSB_WHDR0_DEST_SEL_MASK I40E_MASK(0xF, I40E_MNGSB_WHDR0_DEST_SEL_SHIFT)
sys/dev/pci/if_ixlreg.h
4046
#define I40E_MNGSB_WHDR0_OPCODE_SEL_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT)
sys/dev/pci/if_ixlreg.h
4048
#define I40E_MNGSB_WHDR0_TAG_MASK I40E_MASK(0x7F, I40E_MNGSB_WHDR0_TAG_SHIFT)
sys/dev/pci/if_ixlreg.h
405
#define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1U, I40E_PRTDCB_TFCS_TXOFF7_SHIFT)
sys/dev/pci/if_ixlreg.h
4051
#define I40E_MNGSB_WHDR1_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR1_ADDR_SHIFT)
sys/dev/pci/if_ixlreg.h
4054
#define I40E_MNGSB_WHDR2_LENGTH_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR2_LENGTH_SHIFT)
sys/dev/pci/if_ixlreg.h
4057
#define I40E_GLPCI_CAPSUP_WAKUP_EN_MASK I40E_MASK(0x1U, I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
4061
#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4063
#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4066
#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4069
#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4071
#define I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4074
#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4076
#define I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4079
#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4081
#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4084
#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4086
#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4089
#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
409
#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)
sys/dev/pci/if_ixlreg.h
4091
#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4094
#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4096
#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4099
#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4101
#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4104
#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4106
#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4109
#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4111
#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4114
#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4116
#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4119
#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
412
#define I40E_GLFCOE_RCTL_FCOEVER_MASK I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT)
sys/dev/pci/if_ixlreg.h
4121
#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4124
#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4126
#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4129
#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4131
#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4134
#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4136
#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4139
#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
414
#define I40E_GLFCOE_RCTL_SAVBAD_MASK I40E_MASK(0x1U, I40E_GLFCOE_RCTL_SAVBAD_SHIFT)
sys/dev/pci/if_ixlreg.h
4141
#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4144
#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
4146
#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK I40E_MASK(0x1U, I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
4149
#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_MASK I40E_MASK(0x1U, I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT)
sys/dev/pci/if_ixlreg.h
4151
#define I40E_GLPCI_NPQ_CFG_SMALL_TO_MASK I40E_MASK(0x1U, I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT)
sys/dev/pci/if_ixlreg.h
4153
#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT)
sys/dev/pci/if_ixlreg.h
4155
#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_MASK I40E_MASK(0x3FF, I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT)
sys/dev/pci/if_ixlreg.h
4157
#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT)
sys/dev/pci/if_ixlreg.h
416
#define I40E_GLFCOE_RCTL_ICRC_MASK I40E_MASK(0x1U, I40E_GLFCOE_RCTL_ICRC_SHIFT)
sys/dev/pci/if_ixlreg.h
4160
#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4163
#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4165
#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4168
#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4170
#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4173
#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4175
#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4178
#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
418
#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
4180
#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4183
#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4185
#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4188
#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4190
#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4193
#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT)
sys/dev/pci/if_ixlreg.h
4195
#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFFU, I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT)
sys/dev/pci/if_ixlreg.h
4198
#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT)
sys/dev/pci/if_ixlreg.h
4201
#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT)
sys/dev/pci/if_ixlreg.h
4204
#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT)
sys/dev/pci/if_ixlreg.h
4207
#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_MASK I40E_MASK(0xFFFF, I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT)
sys/dev/pci/if_ixlreg.h
4209
#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_MASK I40E_MASK(0x1U, I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT)
sys/dev/pci/if_ixlreg.h
421
#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)
sys/dev/pci/if_ixlreg.h
4211
#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_MASK I40E_MASK(0x1U, I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT)
sys/dev/pci/if_ixlreg.h
4214
#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_MASK I40E_MASK(0x1U, I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4218
#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4222
#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4226
#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4229
#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT)
sys/dev/pci/if_ixlreg.h
423
#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1U, I40E_GL_FWSTS_FWRI_SHIFT)
sys/dev/pci/if_ixlreg.h
4232
#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT)
sys/dev/pci/if_ixlreg.h
4235
#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT)
sys/dev/pci/if_ixlreg.h
4237
#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_MASK I40E_MASK(0x1U, I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
4239
#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_MASK I40E_MASK(0x1U, I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
4241
#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_MASK I40E_MASK(0x1U, I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
4243
#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_MASK I40E_MASK(0x1U, I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
4245
#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_MASK I40E_MASK(0x1U, I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
4247
#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_MASK I40E_MASK(0x1U, I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
425
#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
sys/dev/pci/if_ixlreg.h
4250
#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT)
sys/dev/pci/if_ixlreg.h
4253
#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT)
sys/dev/pci/if_ixlreg.h
4256
#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_MASK I40E_MASK(0x1U, I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
4260
#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4264
#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4268
#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4272
#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
4274
#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
4278
#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
428
#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1U, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4282
#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4286
#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1U, I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT)
sys/dev/pci/if_ixlreg.h
4288
#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1U, I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT)
sys/dev/pci/if_ixlreg.h
4290
#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1U, I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT)
sys/dev/pci/if_ixlreg.h
4292
#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1U, I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT)
sys/dev/pci/if_ixlreg.h
4294
#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1U, I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
4298
#define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT)
sys/dev/pci/if_ixlreg.h
430
#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)
sys/dev/pci/if_ixlreg.h
4300
#define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK I40E_MASK(0x1U, I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
4303
#define I40E_PFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_AEQALLOC_AECOUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4306
#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
sys/dev/pci/if_ixlreg.h
4309
#define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT)
sys/dev/pci/if_ixlreg.h
4312
#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1U, I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
4314
#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT)
sys/dev/pci/if_ixlreg.h
4316
#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT)
sys/dev/pci/if_ixlreg.h
4318
#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1U, I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
432
#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)
sys/dev/pci/if_ixlreg.h
4321
#define I40E_PFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQACK_PECQID_SHIFT)
sys/dev/pci/if_ixlreg.h
4324
#define I40E_PFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQARM_PECQID_SHIFT)
sys/dev/pci/if_ixlreg.h
4327
#define I40E_PFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPDB_WQHEAD_SHIFT)
sys/dev/pci/if_ixlreg.h
4330
#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4332
#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFFU, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4335
#define I40E_PFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPTAIL_WQTAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
4337
#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1U, I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
434
#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT)
sys/dev/pci/if_ixlreg.h
4340
#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4343
#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4346
#define I40E_PFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_PFPE_IPCONFIG0_PEIPID_SHIFT)
sys/dev/pci/if_ixlreg.h
4348
#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1U, I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
4351
#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
sys/dev/pci/if_ixlreg.h
4354
#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
4357
#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
sys/dev/pci/if_ixlreg.h
436
#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT)
sys/dev/pci/if_ixlreg.h
4360
#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1U, I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT)
sys/dev/pci/if_ixlreg.h
4362
#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1U, I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT)
sys/dev/pci/if_ixlreg.h
4364
#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1U, I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT)
sys/dev/pci/if_ixlreg.h
4366
#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1U, I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT)
sys/dev/pci/if_ixlreg.h
4368
#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1U, I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
4371
#define I40E_PFPE_UDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_PFPE_UDAUCFBQPN_QPN_SHIFT)
sys/dev/pci/if_ixlreg.h
4373
#define I40E_PFPE_UDAUCFBQPN_VALID_MASK I40E_MASK(0x1U, I40E_PFPE_UDAUCFBQPN_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
4376
#define I40E_PFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_PFPE_WQEALLOC_PEQPID_SHIFT)
sys/dev/pci/if_ixlreg.h
4378
#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
sys/dev/pci/if_ixlreg.h
438
#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT)
sys/dev/pci/if_ixlreg.h
4381
#define I40E_PRTDCB_RLPMC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RLPMC_TC2PFC_SHIFT)
sys/dev/pci/if_ixlreg.h
4385
#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT)
sys/dev/pci/if_ixlreg.h
4388
#define I40E_PRTDCB_TCPMC_RLPM_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT)
sys/dev/pci/if_ixlreg.h
4390
#define I40E_PRTDCB_TCPMC_RLPM_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT)
sys/dev/pci/if_ixlreg.h
4392
#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_MASK I40E_MASK(0x1U, I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4395
#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4397
#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4399
#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4401
#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4404
#define I40E_PRTPE_RUPM_CNTR_COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4407
#define I40E_PRTPE_RUPM_CTL_LLTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CTL_LLTC_SHIFT)
sys/dev/pci/if_ixlreg.h
4409
#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_MASK I40E_MASK(0x1U, I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4412
#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT)
sys/dev/pci/if_ixlreg.h
4415
#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT)
sys/dev/pci/if_ixlreg.h
4418
#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT)
sys/dev/pci/if_ixlreg.h
442
#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
4420
#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT)
sys/dev/pci/if_ixlreg.h
4422
#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_MASK I40E_MASK(0x1U, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
4425
#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4427
#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4429
#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4431
#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4434
#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4436
#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4438
#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
444
#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
sys/dev/pci/if_ixlreg.h
4440
#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4443
#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4445
#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4447
#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4449
#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4452
#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT)
sys/dev/pci/if_ixlreg.h
4454
#define I40E_PRTPE_RUPM_THRES_MAXSPADS_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT)
sys/dev/pci/if_ixlreg.h
4456
#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT)
sys/dev/pci/if_ixlreg.h
446
#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
sys/dev/pci/if_ixlreg.h
4460
#define I40E_VFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC_AECOUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
4464
#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
sys/dev/pci/if_ixlreg.h
4468
#define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT)
sys/dev/pci/if_ixlreg.h
4472
#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1U, I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
4474
#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT)
sys/dev/pci/if_ixlreg.h
4476
#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT)
sys/dev/pci/if_ixlreg.h
4478
#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1U, I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
448
#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
sys/dev/pci/if_ixlreg.h
4482
#define I40E_VFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK_PECQID_SHIFT)
sys/dev/pci/if_ixlreg.h
4486
#define I40E_VFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM_PECQID_SHIFT)
sys/dev/pci/if_ixlreg.h
4490
#define I40E_VFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB_WQHEAD_SHIFT)
sys/dev/pci/if_ixlreg.h
4494
#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4496
#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFFU, I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
450
#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
sys/dev/pci/if_ixlreg.h
4500
#define I40E_VFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL_WQTAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
4502
#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1U, I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
4506
#define I40E_VFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG0_PEIPID_SHIFT)
sys/dev/pci/if_ixlreg.h
4508
#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1U, I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
4512
#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
sys/dev/pci/if_ixlreg.h
4516
#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
452
#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
sys/dev/pci/if_ixlreg.h
4520
#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
sys/dev/pci/if_ixlreg.h
4524
#define I40E_VFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC_PEQPID_SHIFT)
sys/dev/pci/if_ixlreg.h
4526
#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
sys/dev/pci/if_ixlreg.h
4530
#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
sys/dev/pci/if_ixlreg.h
4534
#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4538
#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
454
#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT)
sys/dev/pci/if_ixlreg.h
4542
#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4546
#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4550
#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4554
#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4558
#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
456
#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT)
sys/dev/pci/if_ixlreg.h
4562
#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4566
#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4570
#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4574
#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
sys/dev/pci/if_ixlreg.h
4578
#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
458
#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4582
#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4586
#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4590
#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4594
#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4598
#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
460
#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
4602
#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
sys/dev/pci/if_ixlreg.h
4606
#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4610
#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4614
#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4618
#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
462
#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
sys/dev/pci/if_ixlreg.h
4622
#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
sys/dev/pci/if_ixlreg.h
4626
#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4630
#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4634
#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4638
#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
464
#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
sys/dev/pci/if_ixlreg.h
4642
#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4646
#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4650
#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4654
#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4658
#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
466
#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT)
sys/dev/pci/if_ixlreg.h
4662
#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4666
#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
sys/dev/pci/if_ixlreg.h
4670
#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4674
#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4678
#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4682
#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4686
#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
469
#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
4690
#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4694
#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
sys/dev/pci/if_ixlreg.h
4698
#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4702
#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4706
#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
471
#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
sys/dev/pci/if_ixlreg.h
4710
#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4714
#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4718
#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4722
#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4726
#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
473
#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1U, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
sys/dev/pci/if_ixlreg.h
4730
#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4734
#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4738
#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4742
#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4746
#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4750
#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4754
#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4758
#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
476
#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT)
sys/dev/pci/if_ixlreg.h
4762
#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4766
#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4770
#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4774
#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4778
#define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT)
sys/dev/pci/if_ixlreg.h
4782
#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT)
sys/dev/pci/if_ixlreg.h
4786
#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
sys/dev/pci/if_ixlreg.h
479
#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT)
sys/dev/pci/if_ixlreg.h
4790
#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
sys/dev/pci/if_ixlreg.h
4794
#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4798
#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4802
#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4806
#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4810
#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4814
#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4818
#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4822
#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4825
#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4828
#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
483
#define I40E_GLGEN_I2CCMD_DATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT)
sys/dev/pci/if_ixlreg.h
4831
#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4834
#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4837
#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT)
sys/dev/pci/if_ixlreg.h
4840
#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT)
sys/dev/pci/if_ixlreg.h
4843
#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4846
#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT)
sys/dev/pci/if_ixlreg.h
4849
#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT)
sys/dev/pci/if_ixlreg.h
485
#define I40E_GLGEN_I2CCMD_REGADD_MASK I40E_MASK(0xFF, I40E_GLGEN_I2CCMD_REGADD_SHIFT)
sys/dev/pci/if_ixlreg.h
4852
#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT)
sys/dev/pci/if_ixlreg.h
4855
#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4858
#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4861
#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4864
#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT)
sys/dev/pci/if_ixlreg.h
4867
#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT)
sys/dev/pci/if_ixlreg.h
487
#define I40E_GLGEN_I2CCMD_PHYADD_MASK I40E_MASK(0x7, I40E_GLGEN_I2CCMD_PHYADD_SHIFT)
sys/dev/pci/if_ixlreg.h
4870
#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT)
sys/dev/pci/if_ixlreg.h
4873
#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4876
#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4879
#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4882
#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4885
#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4888
#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
489
#define I40E_GLGEN_I2CCMD_OP_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CCMD_OP_SHIFT)
sys/dev/pci/if_ixlreg.h
4892
#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
sys/dev/pci/if_ixlreg.h
4896
#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4900
#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4904
#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4908
#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
491
#define I40E_GLGEN_I2CCMD_RESET_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CCMD_RESET_SHIFT)
sys/dev/pci/if_ixlreg.h
4912
#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4916
#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4920
#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4924
#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4928
#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
493
#define I40E_GLGEN_I2CCMD_R_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CCMD_R_SHIFT)
sys/dev/pci/if_ixlreg.h
4932
#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4936
#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
sys/dev/pci/if_ixlreg.h
4940
#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4944
#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4948
#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
495
#define I40E_GLGEN_I2CCMD_E_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CCMD_E_SHIFT)
sys/dev/pci/if_ixlreg.h
4952
#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4956
#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4960
#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4964
#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
sys/dev/pci/if_ixlreg.h
4968
#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4972
#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4976
#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
4980
#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4984
#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
sys/dev/pci/if_ixlreg.h
4988
#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
499
#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT)
sys/dev/pci/if_ixlreg.h
4992
#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
4996
#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5000
#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5004
#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5008
#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
501
#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK I40E_MASK(0x7, I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT)
sys/dev/pci/if_ixlreg.h
5012
#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5016
#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5020
#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5024
#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5028
#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
sys/dev/pci/if_ixlreg.h
503
#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT)
sys/dev/pci/if_ixlreg.h
5032
#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5036
#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5040
#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5044
#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5048
#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
505
#define I40E_GLGEN_I2CPARAMS_CLK_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_CLK_SHIFT)
sys/dev/pci/if_ixlreg.h
5052
#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5056
#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
sys/dev/pci/if_ixlreg.h
5060
#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5064
#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5068
#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
507
#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT)
sys/dev/pci/if_ixlreg.h
5072
#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5076
#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5080
#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5084
#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5088
#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
509
#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT)
sys/dev/pci/if_ixlreg.h
5092
#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5096
#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5100
#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5104
#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5108
#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
511
#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT)
sys/dev/pci/if_ixlreg.h
5112
#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5116
#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5120
#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5124
#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5128
#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
sys/dev/pci/if_ixlreg.h
513
#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT)
sys/dev/pci/if_ixlreg.h
5132
#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5136
#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5140
#define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT)
sys/dev/pci/if_ixlreg.h
5144
#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT)
sys/dev/pci/if_ixlreg.h
5148
#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
sys/dev/pci/if_ixlreg.h
515
#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT)
sys/dev/pci/if_ixlreg.h
5152
#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
sys/dev/pci/if_ixlreg.h
5156
#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5160
#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5164
#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5168
#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
sys/dev/pci/if_ixlreg.h
517
#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
5172
#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5176
#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5180
#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
sys/dev/pci/if_ixlreg.h
5184
#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
sys/dev/pci/if_ixlreg.h
5187
#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_MASK I40E_MASK(0x1U, I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT)
sys/dev/pci/if_ixlreg.h
519
#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK I40E_MASK(0x1U, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT)
sys/dev/pci/if_ixlreg.h
5191
#define I40E_GLQF_APBVT_APBVT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_APBVT_APBVT_SHIFT)
sys/dev/pci/if_ixlreg.h
5195
#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK I40E_MASK(0x3F, I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
5199
#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT)
sys/dev/pci/if_ixlreg.h
5202
#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT)
sys/dev/pci/if_ixlreg.h
5204
#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT)
sys/dev/pci/if_ixlreg.h
5207
#define I40E_PFQF_CTL_2_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEHSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
5209
#define I40E_PFQF_CTL_2_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
5214
#define I40E_X722_PFQF_HLUT_LUT0_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT0_SHIFT)
sys/dev/pci/if_ixlreg.h
5216
#define I40E_X722_PFQF_HLUT_LUT1_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT1_SHIFT)
sys/dev/pci/if_ixlreg.h
5218
#define I40E_X722_PFQF_HLUT_LUT2_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT2_SHIFT)
sys/dev/pci/if_ixlreg.h
522
#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1U, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
5220
#define I40E_X722_PFQF_HLUT_LUT3_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT3_SHIFT)
sys/dev/pci/if_ixlreg.h
5224
#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1U, I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
sys/dev/pci/if_ixlreg.h
5226
#define I40E_PFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_0_SHIFT)
sys/dev/pci/if_ixlreg.h
5228
#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1U, I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
sys/dev/pci/if_ixlreg.h
5230
#define I40E_PFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_1_SHIFT)
sys/dev/pci/if_ixlreg.h
5232
#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1U, I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
sys/dev/pci/if_ixlreg.h
5234
#define I40E_PFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_2_SHIFT)
sys/dev/pci/if_ixlreg.h
5236
#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1U, I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
sys/dev/pci/if_ixlreg.h
5238
#define I40E_PFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_3_SHIFT)
sys/dev/pci/if_ixlreg.h
5240
#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1U, I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
sys/dev/pci/if_ixlreg.h
5242
#define I40E_PFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_4_SHIFT)
sys/dev/pci/if_ixlreg.h
5244
#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1U, I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
sys/dev/pci/if_ixlreg.h
5246
#define I40E_PFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_5_SHIFT)
sys/dev/pci/if_ixlreg.h
5248
#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1U, I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
sys/dev/pci/if_ixlreg.h
5250
#define I40E_PFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_6_SHIFT)
sys/dev/pci/if_ixlreg.h
5252
#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1U, I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
sys/dev/pci/if_ixlreg.h
5254
#define I40E_PFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_7_SHIFT)
sys/dev/pci/if_ixlreg.h
5256
#define I40E_VSIQF_CTL_RSS_LUT_TYPE_MASK I40E_MASK(0x1U, I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
526
#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT)
sys/dev/pci/if_ixlreg.h
5260
#define I40E_VSIQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_0_SHIFT)
sys/dev/pci/if_ixlreg.h
5262
#define I40E_VSIQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_1_SHIFT)
sys/dev/pci/if_ixlreg.h
5264
#define I40E_VSIQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_2_SHIFT)
sys/dev/pci/if_ixlreg.h
5266
#define I40E_VSIQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_3_SHIFT)
sys/dev/pci/if_ixlreg.h
5270
#define I40E_VSIQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT0_SHIFT)
sys/dev/pci/if_ixlreg.h
5272
#define I40E_VSIQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT1_SHIFT)
sys/dev/pci/if_ixlreg.h
5274
#define I40E_VSIQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT2_SHIFT)
sys/dev/pci/if_ixlreg.h
5276
#define I40E_VSIQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT3_SHIFT)
sys/dev/pci/if_ixlreg.h
5279
#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_MASK I40E_MASK(0x1U, I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT)
sys/dev/pci/if_ixlreg.h
528
#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1U, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
sys/dev/pci/if_ixlreg.h
5282
#define I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT)
sys/dev/pci/if_ixlreg.h
5284
#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)
sys/dev/pci/if_ixlreg.h
5286
#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1U, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
sys/dev/pci/if_ixlreg.h
5289
#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
5292
#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
sys/dev/pci/if_ixlreg.h
5295
#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
sys/dev/pci/if_ixlreg.h
5298
#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1U, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
sys/dev/pci/if_ixlreg.h
530
#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
sys/dev/pci/if_ixlreg.h
5300
#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)
sys/dev/pci/if_ixlreg.h
5302
#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)
sys/dev/pci/if_ixlreg.h
5304
#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1U, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
5307
#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT)
sys/dev/pci/if_ixlreg.h
5310
#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT)
sys/dev/pci/if_ixlreg.h
5313
#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
sys/dev/pci/if_ixlreg.h
5316
#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
5318
#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFFU, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
sys/dev/pci/if_ixlreg.h
532
#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT)
sys/dev/pci/if_ixlreg.h
5321
#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
sys/dev/pci/if_ixlreg.h
5323
#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1U, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
5326
#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
sys/dev/pci/if_ixlreg.h
5328
#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1U, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
sys/dev/pci/if_ixlreg.h
5331
#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
sys/dev/pci/if_ixlreg.h
5334
#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
sys/dev/pci/if_ixlreg.h
5337
#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
sys/dev/pci/if_ixlreg.h
5340
#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
sys/dev/pci/if_ixlreg.h
5342
#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
sys/dev/pci/if_ixlreg.h
536
#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1U, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT)
sys/dev/pci/if_ixlreg.h
538
#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
540
#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT)
sys/dev/pci/if_ixlreg.h
542
#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT)
sys/dev/pci/if_ixlreg.h
544
#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT)
sys/dev/pci/if_ixlreg.h
546
#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT)
sys/dev/pci/if_ixlreg.h
548
#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
550
#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK I40E_MASK(0x1U, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT)
sys/dev/pci/if_ixlreg.h
554
#define I40E_GLGEN_MSCA_MDIADD_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT)
sys/dev/pci/if_ixlreg.h
556
#define I40E_GLGEN_MSCA_DEVADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_DEVADD_SHIFT)
sys/dev/pci/if_ixlreg.h
558
#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT)
sys/dev/pci/if_ixlreg.h
560
#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)
sys/dev/pci/if_ixlreg.h
562
#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)
sys/dev/pci/if_ixlreg.h
564
#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1U, I40E_GLGEN_MSCA_MDICMD_SHIFT)
sys/dev/pci/if_ixlreg.h
566
#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1U, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
sys/dev/pci/if_ixlreg.h
570
#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
sys/dev/pci/if_ixlreg.h
572
#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFFU, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
sys/dev/pci/if_ixlreg.h
575
#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
577
#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
580
#define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
sys/dev/pci/if_ixlreg.h
582
#define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
584
#define I40E_GLGEN_RSTAT_CORERCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_CORERCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
586
#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
588
#define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
590
#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT)
sys/dev/pci/if_ixlreg.h
593
#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
sys/dev/pci/if_ixlreg.h
595
#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1U, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
598
#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1U, I40E_GLGEN_RTRIG_CORER_SHIFT)
sys/dev/pci/if_ixlreg.h
600
#define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1U, I40E_GLGEN_RTRIG_GLOBR_SHIFT)
sys/dev/pci/if_ixlreg.h
602
#define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1U, I40E_GLGEN_RTRIG_EMPFWR_SHIFT)
sys/dev/pci/if_ixlreg.h
605
#define I40E_GLGEN_STAT_HWRSVD0_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT)
sys/dev/pci/if_ixlreg.h
607
#define I40E_GLGEN_STAT_DCBEN_MASK I40E_MASK(0x1U, I40E_GLGEN_STAT_DCBEN_SHIFT)
sys/dev/pci/if_ixlreg.h
609
#define I40E_GLGEN_STAT_VTEN_MASK I40E_MASK(0x1U, I40E_GLGEN_STAT_VTEN_SHIFT)
sys/dev/pci/if_ixlreg.h
611
#define I40E_GLGEN_STAT_FCOEN_MASK I40E_MASK(0x1U, I40E_GLGEN_STAT_FCOEN_SHIFT)
sys/dev/pci/if_ixlreg.h
613
#define I40E_GLGEN_STAT_EVBEN_MASK I40E_MASK(0x1U, I40E_GLGEN_STAT_EVBEN_SHIFT)
sys/dev/pci/if_ixlreg.h
615
#define I40E_GLGEN_STAT_HWRSVD1_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT)
sys/dev/pci/if_ixlreg.h
619
#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT)
sys/dev/pci/if_ixlreg.h
622
#define I40E_GLVFGEN_TIMER_GTIME_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT)
sys/dev/pci/if_ixlreg.h
625
#define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1U, I40E_PFGEN_CTRL_PFSWR_SHIFT)
sys/dev/pci/if_ixlreg.h
628
#define I40E_PFGEN_DRUN_DRVUNLD_MASK I40E_MASK(0x1U, I40E_PFGEN_DRUN_DRVUNLD_SHIFT)
sys/dev/pci/if_ixlreg.h
631
#define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
634
#define I40E_PFGEN_STATE_RESERVED_0_MASK I40E_MASK(0x1U, I40E_PFGEN_STATE_RESERVED_0_SHIFT)
sys/dev/pci/if_ixlreg.h
636
#define I40E_PFGEN_STATE_PFFCEN_MASK I40E_MASK(0x1U, I40E_PFGEN_STATE_PFFCEN_SHIFT)
sys/dev/pci/if_ixlreg.h
638
#define I40E_PFGEN_STATE_PFLINKEN_MASK I40E_MASK(0x1U, I40E_PFGEN_STATE_PFLINKEN_SHIFT)
sys/dev/pci/if_ixlreg.h
640
#define I40E_PFGEN_STATE_PFSCEN_MASK I40E_MASK(0x1U, I40E_PFGEN_STATE_PFSCEN_SHIFT)
sys/dev/pci/if_ixlreg.h
643
#define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1U, I40E_PRTGEN_CNF_PORT_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
645
#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK I40E_MASK(0x1U, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
647
#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK I40E_MASK(0x1U, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT)
sys/dev/pci/if_ixlreg.h
650
#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK I40E_MASK(0x1U, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT)
sys/dev/pci/if_ixlreg.h
653
#define I40E_PRTGEN_STATUS_PORT_VALID_MASK I40E_MASK(0x1U, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT)
sys/dev/pci/if_ixlreg.h
655
#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK I40E_MASK(0x1U, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT)
sys/dev/pci/if_ixlreg.h
659
#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT)
sys/dev/pci/if_ixlreg.h
663
#define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1U, I40E_VPGEN_VFRSTAT_VFRD_SHIFT)
sys/dev/pci/if_ixlreg.h
667
#define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1U, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)
sys/dev/pci/if_ixlreg.h
671
#define I40E_VSIGEN_RSTAT_VMRD_MASK I40E_MASK(0x1U, I40E_VSIGEN_RSTAT_VMRD_SHIFT)
sys/dev/pci/if_ixlreg.h
675
#define I40E_VSIGEN_RTRIG_VMSWR_MASK I40E_MASK(0x1U, I40E_VSIGEN_RTRIG_VMSWR_SHIFT)
sys/dev/pci/if_ixlreg.h
679
#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
683
#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
686
#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
69
#define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
sys/dev/pci/if_ixlreg.h
690
#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
694
#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
697
#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
700
#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
703
#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
707
#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
711
#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
713
#define I40E_GLHMC_FSIAVCNT_RSVD_MASK I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT)
sys/dev/pci/if_ixlreg.h
716
#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
719
#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
72
#define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)
sys/dev/pci/if_ixlreg.h
723
#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
727
#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
730
#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
733
#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
736
#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT)
sys/dev/pci/if_ixlreg.h
740
#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
744
#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
747
#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
75
#define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)
sys/dev/pci/if_ixlreg.h
751
#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
753
#define I40E_GLHMC_LANTXBASE_RSVD_MASK I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT)
sys/dev/pci/if_ixlreg.h
757
#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT)
sys/dev/pci/if_ixlreg.h
760
#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT)
sys/dev/pci/if_ixlreg.h
764
#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT)
sys/dev/pci/if_ixlreg.h
768
#define I40E_GLHMC_SDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT)
sys/dev/pci/if_ixlreg.h
770
#define I40E_GLHMC_SDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT)
sys/dev/pci/if_ixlreg.h
773
#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT)
sys/dev/pci/if_ixlreg.h
776
#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT)
sys/dev/pci/if_ixlreg.h
778
#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK I40E_MASK(0x1U, I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT)
sys/dev/pci/if_ixlreg.h
78
#define I40E_GL_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT)
sys/dev/pci/if_ixlreg.h
780
#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK I40E_MASK(0xF, I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
782
#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
784
#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK I40E_MASK(0x1U, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT)
sys/dev/pci/if_ixlreg.h
787
#define I40E_PFHMC_PDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
sys/dev/pci/if_ixlreg.h
789
#define I40E_PFHMC_PDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
sys/dev/pci/if_ixlreg.h
792
#define I40E_PFHMC_SDCMD_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT)
sys/dev/pci/if_ixlreg.h
794
#define I40E_PFHMC_SDCMD_PMSDWR_MASK I40E_MASK(0x1U, I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
sys/dev/pci/if_ixlreg.h
797
#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT)
sys/dev/pci/if_ixlreg.h
800
#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK I40E_MASK(0x1U, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)
sys/dev/pci/if_ixlreg.h
802
#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK I40E_MASK(0x1U, I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
804
#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT)
sys/dev/pci/if_ixlreg.h
806
#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT)
sys/dev/pci/if_ixlreg.h
81
#define I40E_GL_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT)
sys/dev/pci/if_ixlreg.h
810
#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT)
sys/dev/pci/if_ixlreg.h
813
#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK I40E_MASK(0x1U, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
815
#define I40E_GL_UFUSE_NIC_ID_MASK I40E_MASK(0x1U, I40E_GL_UFUSE_NIC_ID_SHIFT)
sys/dev/pci/if_ixlreg.h
817
#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK I40E_MASK(0x1U, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT)
sys/dev/pci/if_ixlreg.h
819
#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK I40E_MASK(0x1U, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT)
sys/dev/pci/if_ixlreg.h
822
#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
824
#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
826
#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
828
#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
830
#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
832
#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
834
#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
836
#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
838
#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
84
#define I40E_GL_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT)
sys/dev/pci/if_ixlreg.h
840
#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
842
#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
844
#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
846
#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
848
#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
850
#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
852
#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
854
#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
856
#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
858
#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
860
#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
862
#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
864
#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
866
#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
868
#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
87
#define I40E_GL_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT)
sys/dev/pci/if_ixlreg.h
870
#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
872
#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
874
#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
876
#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
878
#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
880
#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1U, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
883
#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT)
sys/dev/pci/if_ixlreg.h
885
#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1U, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
888
#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
890
#define I40E_PFINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_AEQCTL_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
892
#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
894
#define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
896
#define I40E_PFINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1U, I40E_PFINT_AEQCTL_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
90
#define I40E_GL_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT)
sys/dev/pci/if_ixlreg.h
900
#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
902
#define I40E_PFINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
904
#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
906
#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
908
#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT)
sys/dev/pci/if_ixlreg.h
910
#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
912
#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1U, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)
sys/dev/pci/if_ixlreg.h
915
#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK I40E_MASK(0x1U, I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT)
sys/dev/pci/if_ixlreg.h
917
#define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1U, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT)
sys/dev/pci/if_ixlreg.h
919
#define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK I40E_MASK(0x1U, I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT)
sys/dev/pci/if_ixlreg.h
92
#define I40E_GL_ATQLEN_ATQVFE_MASK I40E_MASK(0x1U, I40E_GL_ATQLEN_ATQVFE_SHIFT)
sys/dev/pci/if_ixlreg.h
922
#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
sys/dev/pci/if_ixlreg.h
924
#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT)
sys/dev/pci/if_ixlreg.h
926
#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
sys/dev/pci/if_ixlreg.h
928
#define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
930
#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
932
#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
934
#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
936
#define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)
sys/dev/pci/if_ixlreg.h
94
#define I40E_GL_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1U, I40E_GL_ATQLEN_ATQOVFL_SHIFT)
sys/dev/pci/if_ixlreg.h
940
#define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTLN_INTENA_SHIFT)
sys/dev/pci/if_ixlreg.h
942
#define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT)
sys/dev/pci/if_ixlreg.h
944
#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
sys/dev/pci/if_ixlreg.h
946
#define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
948
#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)
sys/dev/pci/if_ixlreg.h
950
#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
952
#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
sys/dev/pci/if_ixlreg.h
954
#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1U, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT)
sys/dev/pci/if_ixlreg.h
957
#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
959
#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
96
#define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1U, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
sys/dev/pci/if_ixlreg.h
961
#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
963
#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
965
#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
967
#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
969
#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
971
#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
973
#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
975
#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
977
#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
979
#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
98
#define I40E_GL_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1U, I40E_GL_ATQLEN_ATQENABLE_SHIFT)
sys/dev/pci/if_ixlreg.h
981
#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
983
#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
985
#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
987
#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
989
#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
991
#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
993
#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
995
#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
997
#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT)
sys/dev/pci/if_ixlreg.h
999
#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1U, I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT)
