sys/arch/sgimips/gio/grtworeg.h

76

#define HQ2_ATTRJUMP (HQ2_BASE + 0x00)

sys/arch/sgimips/gio/grtworeg.h

77

#define HQ2_VERSION (HQ2_BASE + 0x40)

sys/arch/sgimips/gio/grtworeg.h

81

#define HQ2_NUMGE (HQ2_BASE + 0x44)

sys/arch/sgimips/gio/grtworeg.h

82

#define HQ2_FIN1 (HQ2_BASE + 0x48)

sys/arch/sgimips/gio/grtworeg.h

83

#define HQ2_FIN2 (HQ2_BASE + 0x4c)

sys/arch/sgimips/gio/grtworeg.h

84

#define HQ2_DMASYNC (HQ2_BASE + 0x50)

sys/arch/sgimips/gio/grtworeg.h

85

#define HQ2_FIFO_FULL_TIMEOUT (HQ2_BASE + 0x54)

sys/arch/sgimips/gio/grtworeg.h

86

#define HQ2_FIFO_EMPTY_TIMEOUT (HQ2_BASE + 0x58)

sys/arch/sgimips/gio/grtworeg.h

87

#define HQ2_FIFO_FULL (HQ2_BASE + 0x5c)

sys/arch/sgimips/gio/grtworeg.h

88

#define HQ2_FIFO_EMPTY (HQ2_BASE + 0x60)

sys/arch/sgimips/gio/grtworeg.h

89

#define HQ2_GE7_LOAD_UCODE (HQ2_BASE + 0x64)

sys/arch/sgimips/gio/grtworeg.h

90

#define HQ2_GEDMA (HQ2_BASE + 0x68)

sys/arch/sgimips/gio/grtworeg.h

91

#define HQ2_HQ_GEPC (HQ2_BASE + 0x6c)

sys/arch/sgimips/gio/grtworeg.h

92

#define HQ2_GEPC (HQ2_BASE + 0x70)

sys/arch/sgimips/gio/grtworeg.h

93

#define HQ2_INTR (HQ2_BASE + 0x74)

sys/arch/sgimips/gio/grtworeg.h

94

#define HQ2_UNSTALL (HQ2_BASE + 0x78)

sys/arch/sgimips/gio/grtworeg.h

95

#define HQ2_MYSTERY (HQ2_BASE + 0x7c) /* == 0xdeadbeef */

sys/arch/sgimips/gio/grtworeg.h

96

#define HQ2_REFRESH (HQ2_BASE + 0x80)

sys/arch/sgimips/gio/grtworeg.h

97

#define HQ2_FIN3 (HQ2_BASE + 0x100)