sys/arch/arm/amlogic/meson8b_clkc.c

123

uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL);

sys/arch/arm/amlogic/meson8b_clkc.c

165

CLK_WRITE(sc, HHI_SYS_PLL_CNTL, cntl);

sys/arch/arm/amlogic/meson8b_clkc.c

170

} while ((CLK_READ(sc, HHI_SYS_PLL_CNTL) & HHI_SYS_PLL_CNTL_LOCK) == 0);

sys/arch/arm/amlogic/meson8b_clkc.c

185

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */

sys/arch/arm/amlogic/meson8b_clkc.c

186

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */

sys/arch/arm/amlogic/meson8b_clkc.c

187

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */

sys/arch/arm/amlogic/meson8b_clkc.c

189

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */

sys/arch/arm/amlogic/meson8b_clkc.c

190

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */

sys/arch/arm/amlogic/meson8b_clkc.c

195

HHI_SYS_PLL_CNTL, /* reg */

sys/arch/arm/amlogic/mesongxbb_clkc.c

100

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */

sys/arch/arm/amlogic/mesongxbb_clkc.c

101

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */

sys/arch/arm/amlogic/mesongxbb_clkc.c

105

HHI_SYS_PLL_CNTL, /* reg */

sys/arch/arm/amlogic/mesongxbb_clkc.c

96

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */

sys/arch/arm/amlogic/mesongxbb_clkc.c

97

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */

sys/arch/arm/amlogic/mesongxbb_clkc.c

98

MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */