HHI_GCLK_MPEG2
MESON_CLK_GATE(MESON8B_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 8),
MESON_CLK_GATE(MESON8B_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9),
MESON_CLK_GATE(MESON8B_CLOCK_UART2, "uart2", "clk81", HHI_GCLK_MPEG2, 15),
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
HHI_GCLK_MPEG2, /* reg */ \
MESON_CLK_GATE(MESONGXBB_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 8),
MESON_CLK_GATE(MESONGXBB_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9),
MESON_CLK_GATE(MESONGXBB_CLOCK_UART2, "uart2", "clk81", HHI_GCLK_MPEG2, 15),