HHI_GCLK_MPEG0
MESON_CLK_GATE(MESON8B_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
MESON_CLK_GATE(MESON8B_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
MESON_CLK_GATE(MESON8B_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12),
MESON_CLK_GATE(MESON8B_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13),
MESON_CLK_GATE(MESON8B_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14),
MESON_CLK_GATE(MESON8B_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17),
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
HHI_GCLK_MPEG0, /* reg */ \
MESON_CLK_GATE(MESONGXBB_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
MESON_CLK_GATE(MESONGXBB_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
MESON_CLK_GATE(MESONGXBB_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12),
MESON_CLK_GATE(MESONGXBB_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13),
MESON_CLK_GATE(MESONGXBB_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14),
MESON_CLK_GATE(MESONGXBB_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_A, "sd_emmc_a", "clk81", HHI_GCLK_MPEG0, 24),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_B, "sd_emmc_b", "clk81", HHI_GCLK_MPEG0, 25),
MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_C, "sd_emmc_c", "clk81", HHI_GCLK_MPEG0, 26),