sys/arch/arm/nvidia/tegra_drm_mode.c

1010

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE2_REG, state2);

sys/arch/arm/nvidia/tegra_drm_mode.c

1012

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE1_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

1017

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0);

sys/arch/arm/nvidia/tegra_drm_mode.c

1019

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

1025

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_STATE0_REG, 0);

sys/arch/arm/nvidia/tegra_drm_mode.c

1038

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_CTRL_REG, ctrl);

sys/arch/arm/nvidia/tegra_drm_mode.c

1049

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

1053

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_AUDIO_N_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

1058

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_SPARE_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

1067

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1070

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1077

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1083

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1086

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1090

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1098

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1101

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1105

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1108

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1112

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1116

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

1118

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1121

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1124

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0);

sys/arch/arm/nvidia/tegra_drm_mode.c

1126

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1128

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1130

HDMI_WRITE(tegra_encoder,

sys/arch/arm/nvidia/tegra_drm_mode.c

1132

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_HDMI_ACR_CTRL_REG, 0);

sys/arch/arm/nvidia/tegra_drm_mode.c

933

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL0_REG, tmds->sor_pll0);

sys/arch/arm/nvidia/tegra_drm_mode.c

934

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PLL1_REG, tmds->sor_pll1);

sys/arch/arm/nvidia/tegra_drm_mode.c

935

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

937

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_PE_CURRENT_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

939

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

941

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PAD_CTLS0_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

945

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_REFCLK_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

963

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST0_REG, inst);

sys/arch/arm/nvidia/tegra_drm_mode.c

964

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_SEQ_INST8_REG, inst);

sys/arch/arm/nvidia/tegra_drm_mode.c

970

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_INPUT_CONTROL_REG, input_ctrl);

sys/arch/arm/nvidia/tegra_drm_mode.c

983

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG,

sys/arch/arm/nvidia/tegra_drm_mode.c

987

HDMI_WRITE(tegra_encoder, HDMI_NV_PDISP_SOR_PWR_REG,

sys/arch/arm/sunxi/sunxi_hdmi.c

1010

HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

1031

HDMI_WRITE(sc, SUNXI_HDMI_ADMA_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

1041

HDMI_WRITE(sc, SUNXI_HDMI_AUD_FMT_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

1044

HDMI_WRITE(sc, SUNXI_HDMI_AUD_PCM_CTRL_REG, 0x76543210);

sys/arch/arm/sunxi/sunxi_hdmi.c

1049

HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTS_REG, cts);

sys/arch/arm/sunxi/sunxi_hdmi.c

1050

HDMI_WRITE(sc, SUNXI_HDMI_AUD_N_REG, n);

sys/arch/arm/sunxi/sunxi_hdmi.c

1055

HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS0_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

1064

HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

1069

HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

1152

HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, intsts);

sys/arch/arm/sunxi/sunxi_hdmi.c

250

HDMI_WRITE(sc, j, 0);

sys/arch/arm/sunxi/sunxi_hdmi.c

342

HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

348

HDMI_WRITE(sc, SUNXI_HDMI_DDC_SLAVE_ADDR_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

352

HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

354

HDMI_WRITE(sc, SUNXI_HDMI_DDC_BYTE_COUNTER_REG, len);

sys/arch/arm/sunxi/sunxi_hdmi.c

356

HDMI_WRITE(sc, SUNXI_HDMI_DDC_COMMAND_REG, type);

sys/arch/arm/sunxi/sunxi_hdmi.c

360

HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

391

HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

397

HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

399

HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_COMMAND_REG,

sys/arch/arm/sunxi/sunxi_hdmi.c

405

HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

453

HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, 0);

sys/arch/arm/sunxi/sunxi_hdmi.c

454

HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG,

sys/arch/arm/sunxi/sunxi_hdmi.c

466

HDMI_WRITE(sc, SUNXI_HDMI_DDC_CLOCK_REG,

sys/arch/arm/sunxi/sunxi_hdmi.c

470

HDMI_WRITE(sc, SUNXI_HDMI_DDC_DBG_REG, 0x300);

sys/arch/arm/sunxi/sunxi_hdmi.c

472

HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG,

sys/arch/arm/sunxi/sunxi_hdmi.c

476

HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CLOCK_REG,

sys/arch/arm/sunxi/sunxi_hdmi.c

480

HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG,

sys/arch/arm/sunxi/sunxi_hdmi.c

618

HDMI_WRITE(sc, SUNXI_HDMI_CTRL_REG, SUNXI_HDMI_CTRL_MODULE_EN);

sys/arch/arm/sunxi/sunxi_hdmi.c

621

HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0xfe800000);

sys/arch/arm/sunxi/sunxi_hdmi.c

622

HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x00d8c830);

sys/arch/arm/sunxi/sunxi_hdmi.c

624

HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0x7e80000f);

sys/arch/arm/sunxi/sunxi_hdmi.c

625

HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x01ded030);

sys/arch/arm/sunxi/sunxi_hdmi.c

627

HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, dbg0_reg);

sys/arch/arm/sunxi/sunxi_hdmi.c

825

HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

862

HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, 0xffffffff);

sys/arch/arm/sunxi/sunxi_hdmi.c

918

HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, pad_ctrl0);

sys/arch/arm/sunxi/sunxi_hdmi.c

919

HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, pad_ctrl1);

sys/arch/arm/sunxi/sunxi_hdmi.c

920

HDMI_WRITE(sc, SUNXI_HDMI_PLL_CTRL_REG, pll_ctrl);

sys/arch/arm/sunxi/sunxi_hdmi.c

924

HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (0<<21));

sys/arch/arm/sunxi/sunxi_hdmi.c

927

HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (1<<21));

sys/arch/arm/sunxi/sunxi_hdmi.c

952

HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

958

HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_0_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

964

HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_1_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

970

HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_2_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

976

HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_3_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

987

HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_4_REG, val);

sys/arch/arm/sunxi/sunxi_hdmi.c

990

HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT0_REG, 0);

sys/arch/arm/sunxi/sunxi_hdmi.c

991

HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT1_REG, 0);

sys/arch/arm/sunxi/sunxi_hdmi.c

992

HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL0_REG, 0x00005321);

sys/arch/arm/sunxi/sunxi_hdmi.c

993

HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL1_REG, 0x0000000f);