sys/arch/arm/imx/imx51reg.h

250

#define GPIO1_BASE GPIO_BASE(1)

sys/arch/arm/imx/imx51reg.h

251

#define GPIO2_BASE GPIO_BASE(2)

sys/arch/arm/imx/imx51reg.h

252

#define GPIO3_BASE GPIO_BASE(3)

sys/arch/arm/imx/imx51reg.h

253

#define GPIO4_BASE GPIO_BASE(4)

sys/arch/arm/imx/imx51reg.h

254

#define GPIO5_BASE GPIO_BASE(5)

sys/arch/arm/imx/imx51reg.h

255

#define GPIO6_BASE GPIO_BASE(6)

sys/arch/mips/alchemy/au1000.c

186

{ "augpio", { GPIO_BASE, 32 }, { -1, -1 }},

sys/arch/mips/alchemy/au1100.c

184

{ "augpio", { GPIO_BASE, 32 }, { -1, -1 }},

sys/arch/mips/alchemy/au1500.c

187

{ "augpio", { GPIO_BASE, 23 }, { -1, -1 }},

sys/arch/mips/alchemy/au1550.c

187

{ "augpio", { GPIO_BASE, 27 }, { -1, -1 }},

sys/arch/mips/alchemy/dev/augpio.c

107

if (aa->aa_addrs[0] == GPIO_BASE) {

sys/arch/mips/alchemy/dev/augpio.c

77

#define GETGPIO(x) GETREG(GPIO_BASE + (x))

sys/arch/mips/alchemy/dev/augpio.c

78

#define PUTGPIO(x,v) PUTREG(GPIO_BASE + (x), (v))

sys/arch/powerpc/booke/dev/pq3gpio.c

527

GPIO_BASE, GPIO_SIZE },

sys/arch/powerpc/booke/dev/pq3gpio.c

535

GPIO_BASE, GPIO_SIZE },

sys/arch/powerpc/booke/dev/pq3gpio.c

539

GPIO_BASE, GPIO_SIZE },