sys/arch/arm/at91/at91spi.c

186

if (GETREG(sc, SPI_SR) & SPI_SR_RDRF)

sys/arch/arm/at91/at91spi.c

187

(void)GETREG(sc, SPI_RDR);

sys/arch/arm/at91/at91spi.c

205

csr = GETREG(sc, SPI_CSR(0)); /* read register */

sys/arch/arm/at91/at91spi.c

252

if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DR) {

sys/arch/arm/at91/at91spi.c

275

if (((sr = GETREG(sc, SPI_SR)) & (SPI_SR_ENDTX | SPI_SR_ENDRX)) != (SPI_SR_ENDTX | SPI_SR_ENDRX)) {

sys/arch/arm/at91/at91spi.c

339

GETREG(sc, SPI_MR), GETREG(sc, SPI_SR),

sys/arch/arm/at91/at91spi.c

340

GETREG(sc, SPI_IMR), GETREG(sc, SPI_CSR(0))));

sys/arch/arm/at91/at91spi.c

425

if ((imr = GETREG(sc, SPI_IMR)) == 0) {

sys/arch/arm/at91/at91spi.c

431

sr = GETREG(sc, SPI_SR);

sys/arch/mips/alchemy/dev/augpio.c

77

#define GETGPIO(x) GETREG(GPIO_BASE + (x))

sys/arch/mips/alchemy/dev/augpio.c

79

#define GETGPIO2(x) GETREG(GPIO2_BASE + (x))

sys/arch/mips/alchemy/dev/aurtc.c

144

tv->tv_sec = GETREG(PC_COUNTER_READ_0);

sys/arch/mips/alchemy/dev/aurtc.c

160

while (GETREG(PC_COUNTER_CONTROL) & CC_C0S) {

sys/arch/mips/alchemy/dev/aurtc.c

180

while (GETREG(PC_COUNTER_CONTROL) & CC_C0S) {

sys/arch/mips/alchemy/dev/auspi.c

175

reg = GETREG(sc, AUPSC_SPICFG);

sys/arch/mips/alchemy/dev/auspi.c

240

if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DR) {

sys/arch/mips/alchemy/dev/auspi.c

260

if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_TF) {

sys/arch/mips/alchemy/dev/auspi.c

294

if ((GETREG(sc, AUPSC_SPISTAT) & SPISTAT_RE) != 0) {

sys/arch/mips/alchemy/dev/auspi.c

299

data = GETREG(sc, AUPSC_SPITXRX);

sys/arch/mips/alchemy/dev/auspi.c

368

if ((GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DI) == 0) {

sys/arch/mips/alchemy/dev/auspi.c

372

ev = GETREG(sc, AUPSC_SPIEVNT);

sys/arch/mips/atheros/dev/argpio.c

168

reg = GETREG(sc, GPIO_CR);

sys/arch/mips/atheros/dev/argpio.c

217

reg = GETREG(sc, GPIO_CR);

sys/arch/mips/atheros/dev/argpio.c

239

reg = GETREG(sc, GPIO_DO);

sys/arch/mips/atheros/dev/argpio.c

253

return ((GETREG(sc, GPIO_DI) & (1 << pin)) ?

sys/arch/mips/atheros/dev/argpio.c

268

GETREG(sc, GPIO_CR) | INTR(sc->sc_rstpin));

sys/arch/mips/atheros/dev/argpio.c

281

PUTREG(sc, GPIO_CR, GETREG(sc, GPIO_CR) & ~INTR(sc->sc_rstpin));

sys/arch/mips/atheros/dev/arspi.c

219

while (GETREG(sc, ARSPI_REG_CTL) & ARSPI_CTL_BUSY);

sys/arch/mips/atheros/dev/arspi.c

301

ctl = GETREG(sc, ARSPI_REG_CTL);

sys/arch/mips/atheros/dev/arspi.c

354

if ((GETREG(sc, ARSPI_REG_DATA) &

sys/arch/mips/atheros/dev/arspi.c

375

job->job_data = GETREG(sc, ARSPI_REG_DATA);

sys/arch/mips/cavium/dev/octeon_mpi.c

230

return GETREG(sc, offset);

sys/dev/ic/smc90cx6.c

163

} while (!(GETREG(BAHSTAT) & BAH_POR));

sys/dev/ic/smc90cx6.c

261

} while (!(GETREG(BAHSTAT) & BAH_POR));

sys/dev/ic/smc90cx6.c

280

device_xname(sc->sc_dev), GETREG(BAHSTAT));

sys/dev/ic/smc90cx6.c

286

device_xname(sc->sc_dev), GETREG(BAHSTAT));

sys/dev/ic/smc90cx6.c

302

device_xname(sc->sc_dev), GETREG(BAHSTAT));

sys/dev/ic/smc90cx6.c

692

device_xname(sc->sc_dev), buffer, GETREG(BAHSTAT));

sys/dev/ic/smc90cx6.c

703

device_xname(sc->sc_dev), GETREG(BAHSTAT));

sys/dev/ic/smc90cx6.c

733

isr = GETREG(BAHSTAT);

sys/dev/ic/smc90cx6.c

832

GETREG(BAHSTAT));

sys/dev/ic/smc90cx6.c

851

isr = GETREG(BAHSTAT);

sys/dev/marvell/mvspi.c

126

ctl = GETREG(sc, MVSPI_INTCONF_REG);

sys/dev/marvell/mvspi.c

273

ctl = GETREG(sc, MVSPI_CTRL_REG);

sys/dev/marvell/mvspi.c

281

int ctl = GETREG(sc, MVSPI_CTRL_REG);

sys/dev/marvell/mvspi.c

312

ctl = GETREG(sc, MVSPI_CTRL_REG);

sys/dev/marvell/mvspi.c

327

if (GETREG(sc, MVSPI_CTRL_REG) &

sys/dev/marvell/mvspi.c

344

GETREG(sc, MVSPI_DATAIN_REG);