Symbol: GCSC_SB_MSR_BASE
sys/arch/evbmips/loongson/dev/glxreg.h
104
#define GCSC_GLPCI_GLD_MSR_CAP (GCSC_SB_MSR_BASE + 0x00)
sys/arch/evbmips/loongson/dev/glxreg.h
105
#define GCSC_GLPCI_GLD_MSR_CONFIG (GCSC_SB_MSR_BASE + 0x01)
sys/arch/evbmips/loongson/dev/glxreg.h
106
#define GCSC_GLPCI_GLD_MSR_SMI (GCSC_SB_MSR_BASE + 0x02)
sys/arch/evbmips/loongson/dev/glxreg.h
107
#define GCSC_GLPCI_GLD_MSR_ERROR (GCSC_SB_MSR_BASE + 0x03)
sys/arch/evbmips/loongson/dev/glxreg.h
108
#define GCSC_GLPCI_GLD_MSR_PM (GCSC_SB_MSR_BASE + 0x04)
sys/arch/evbmips/loongson/dev/glxreg.h
109
#define GCSC_GLPCI_GLD_MSR_DIAG (GCSC_SB_MSR_BASE + 0x05)
sys/arch/evbmips/loongson/dev/glxreg.h
111
#define GCSC_GLPCI_CTRL (GCSC_SB_MSR_BASE + 0x10)
sys/arch/evbmips/loongson/dev/glxreg.h
112
#define GCSC_GLPCI_R0 (GCSC_SB_MSR_BASE + 0x20)
sys/arch/evbmips/loongson/dev/glxreg.h
113
#define GCSC_GLPCI_R1 (GCSC_SB_MSR_BASE + 0x21)
sys/arch/evbmips/loongson/dev/glxreg.h
114
#define GCSC_GLPCI_R2 (GCSC_SB_MSR_BASE + 0x22)
sys/arch/evbmips/loongson/dev/glxreg.h
115
#define GCSC_GLPCI_R3 (GCSC_SB_MSR_BASE + 0x23)
sys/arch/evbmips/loongson/dev/glxreg.h
116
#define GCSC_GLPCI_R4 (GCSC_SB_MSR_BASE + 0x24)
sys/arch/evbmips/loongson/dev/glxreg.h
117
#define GCSC_GLPCI_R5 (GCSC_SB_MSR_BASE + 0x25)
sys/arch/evbmips/loongson/dev/glxreg.h
118
#define GCSC_GLPCI_R6 (GCSC_SB_MSR_BASE + 0x26)
sys/arch/evbmips/loongson/dev/glxreg.h
119
#define GCSC_GLPCI_R7 (GCSC_SB_MSR_BASE + 0x27)
sys/arch/evbmips/loongson/dev/glxreg.h
120
#define GCSC_GLPCI_R8 (GCSC_SB_MSR_BASE + 0x28)
sys/arch/evbmips/loongson/dev/glxreg.h
121
#define GCSC_GLPCI_R9 (GCSC_SB_MSR_BASE + 0x29)
sys/arch/evbmips/loongson/dev/glxreg.h
122
#define GCSC_GLPCI_R10 (GCSC_SB_MSR_BASE + 0x2a)
sys/arch/evbmips/loongson/dev/glxreg.h
123
#define GCSC_GLPCI_R11 (GCSC_SB_MSR_BASE + 0x2b)
sys/arch/evbmips/loongson/dev/glxreg.h
124
#define GCSC_GLPCI_R12 (GCSC_SB_MSR_BASE + 0x2c)
sys/arch/evbmips/loongson/dev/glxreg.h
125
#define GCSC_GLPCI_R13 (GCSC_SB_MSR_BASE + 0x2d)
sys/arch/evbmips/loongson/dev/glxreg.h
126
#define GCSC_GLPCI_R14 (GCSC_SB_MSR_BASE + 0x2e)
sys/arch/evbmips/loongson/dev/glxreg.h
127
#define GCSC_GLPCI_R15 (GCSC_SB_MSR_BASE + 0x2f)
sys/arch/evbmips/loongson/dev/glxreg.h
128
#define GCSC_GLPCI_PCIHEAD_BYTE0_3 (GCSC_SB_MSR_BASE + 0x30)
sys/arch/evbmips/loongson/dev/glxreg.h
129
#define GCSC_GLPCI_PCIHEAD_BYTE4_7 (GCSC_SB_MSR_BASE + 0x31)
sys/arch/evbmips/loongson/dev/glxreg.h
130
#define GCSC_GLPCI_PCIHEAD_BYTE8_B (GCSC_SB_MSR_BASE + 0x32)
sys/arch/evbmips/loongson/dev/glxreg.h
131
#define GCSC_GLPCI_PCIHEAD_BYTEC_F (GCSC_SB_MSR_BASE + 0x33)