sys/arch/evbmips/loongson/dev/glxreg.h

164

#define GCSC_IDE_GLD_MSR_CAP (GCSC_IDE_MSR_BASE + 0x00)

sys/arch/evbmips/loongson/dev/glxreg.h

165

#define GCSC_IDE_GLD_MSR_CONFIG (GCSC_IDE_MSR_BASE + 0x01)

sys/arch/evbmips/loongson/dev/glxreg.h

166

#define GCSC_IDE_GLD_MSR_SMI (GCSC_IDE_MSR_BASE + 0x02)

sys/arch/evbmips/loongson/dev/glxreg.h

167

#define GCSC_IDE_GLD_MSR_ERROR (GCSC_IDE_MSR_BASE + 0x03)

sys/arch/evbmips/loongson/dev/glxreg.h

168

#define GCSC_IDE_GLD_MSR_PM (GCSC_IDE_MSR_BASE + 0x04)

sys/arch/evbmips/loongson/dev/glxreg.h

169

#define GCSC_IDE_GLD_MSR_DIAG (GCSC_IDE_MSR_BASE + 0x05)

sys/arch/evbmips/loongson/dev/glxreg.h

171

#define GCSC_IDE_IO_BAR (GCSC_IDE_MSR_BASE + 0x08)

sys/arch/evbmips/loongson/dev/glxreg.h

172

#define GCSC_IDE_CFG (GCSC_IDE_MSR_BASE + 0x10)

sys/arch/evbmips/loongson/dev/glxreg.h

173

#define GCSC_IDE_DTC (GCSC_IDE_MSR_BASE + 0x12)

sys/arch/evbmips/loongson/dev/glxreg.h

174

#define GCSC_IDE_CAST (GCSC_IDE_MSR_BASE + 0x13)

sys/arch/evbmips/loongson/dev/glxreg.h

175

#define GCSC_IDE_ETC (GCSC_IDE_MSR_BASE + 0x14)

sys/arch/evbmips/loongson/dev/glxreg.h

176

#define GCSC_IDE_PM (GCSC_IDE_MSR_BASE + 0x15)