Symbol: GCSC_GLIU_MSR_BASE
sys/arch/evbmips/loongson/dev/glxreg.h
39
#define GCSC_GLIU_GLD_MSR_CAP (GCSC_GLIU_MSR_BASE + 0x00)
sys/arch/evbmips/loongson/dev/glxreg.h
40
#define GCSC_GLIU_GLD_MSR_CONFIG (GCSC_GLIU_MSR_BASE + 0x01)
sys/arch/evbmips/loongson/dev/glxreg.h
41
#define GCSC_GLIU_GLD_MSR_SMI (GCSC_GLIU_MSR_BASE + 0x02)
sys/arch/evbmips/loongson/dev/glxreg.h
42
#define GCSC_GLIU_GLD_MSR_ERROR (GCSC_GLIU_MSR_BASE + 0x03)
sys/arch/evbmips/loongson/dev/glxreg.h
43
#define GCSC_GLIU_GLD_MSR_PM (GCSC_GLIU_MSR_BASE + 0x04)
sys/arch/evbmips/loongson/dev/glxreg.h
44
#define GCSC_GLIU_GLD_MSR_DIAG (GCSC_GLIU_MSR_BASE + 0x05)
sys/arch/evbmips/loongson/dev/glxreg.h
46
#define GCSC_GLIU_P2D_BM0 (GCSC_GLIU_MSR_BASE + 0x20)
sys/arch/evbmips/loongson/dev/glxreg.h
47
#define GCSC_GLIU_P2D_BM1 (GCSC_GLIU_MSR_BASE + 0x21)
sys/arch/evbmips/loongson/dev/glxreg.h
48
#define GCSC_GLIU_P2D_BM2 (GCSC_GLIU_MSR_BASE + 0x22)
sys/arch/evbmips/loongson/dev/glxreg.h
49
#define GCSC_GLIU_P2D_BMK0 (GCSC_GLIU_MSR_BASE + 0x23)
sys/arch/evbmips/loongson/dev/glxreg.h
50
#define GCSC_GLIU_P2D_BMK1 (GCSC_GLIU_MSR_BASE + 0x24)
sys/arch/evbmips/loongson/dev/glxreg.h
51
#define GCSC_GLIU_P2D_BM3 (GCSC_GLIU_MSR_BASE + 0x25)
sys/arch/evbmips/loongson/dev/glxreg.h
52
#define GCSC_GLIU_P2D_BM4 (GCSC_GLIU_MSR_BASE + 0x26)
sys/arch/evbmips/loongson/dev/glxreg.h
54
#define GCSC_GLIU_COH (GCSC_GLIU_MSR_BASE + 0x80)
sys/arch/evbmips/loongson/dev/glxreg.h
55
#define GCSC_GLIU_PAE (GCSC_GLIU_MSR_BASE + 0x81)
sys/arch/evbmips/loongson/dev/glxreg.h
56
#define GCSC_GLIU_ARB (GCSC_GLIU_MSR_BASE + 0x82)
sys/arch/evbmips/loongson/dev/glxreg.h
57
#define GCSC_GLIU_ASMI (GCSC_GLIU_MSR_BASE + 0x83)
sys/arch/evbmips/loongson/dev/glxreg.h
58
#define GCSC_GLIU_AERR (GCSC_GLIU_MSR_BASE + 0x84)
sys/arch/evbmips/loongson/dev/glxreg.h
59
#define GCSC_GLIU_DEBUG (GCSC_GLIU_MSR_BASE + 0x85)
sys/arch/evbmips/loongson/dev/glxreg.h
60
#define GCSC_GLIU_PHY_CAP (GCSC_GLIU_MSR_BASE + 0x86)
sys/arch/evbmips/loongson/dev/glxreg.h
61
#define GCSC_GLIU_NOUT_RESP (GCSC_GLIU_MSR_BASE + 0x87)
sys/arch/evbmips/loongson/dev/glxreg.h
62
#define GCSC_GLIU_NOUT_WDATA (GCSC_GLIU_MSR_BASE + 0x88)
sys/arch/evbmips/loongson/dev/glxreg.h
63
#define GCSC_GLIU_WHOAMI (GCSC_GLIU_MSR_BASE + 0x8b)
sys/arch/evbmips/loongson/dev/glxreg.h
64
#define GCSC_GLIU_SLV_DIS (GCSC_GLIU_MSR_BASE + 0x8c)
sys/arch/evbmips/loongson/dev/glxreg.h
65
#define GCSC_GLIU_STATISTIC_CNT0 (GCSC_GLIU_MSR_BASE + 0xa0)
sys/arch/evbmips/loongson/dev/glxreg.h
66
#define GCSC_GLIU_STATISTIC_MASK0 (GCSC_GLIU_MSR_BASE + 0xa1)
sys/arch/evbmips/loongson/dev/glxreg.h
67
#define GCSC_GLIU_STATISTIC_ACTION0 (GCSC_GLIU_MSR_BASE + 0xa2)
sys/arch/evbmips/loongson/dev/glxreg.h
68
#define GCSC_GLIU_STATISTIC_CNT1 (GCSC_GLIU_MSR_BASE + 0xa4)
sys/arch/evbmips/loongson/dev/glxreg.h
69
#define GCSC_GLIU_STATISTIC_MASK1 (GCSC_GLIU_MSR_BASE + 0xa5)
sys/arch/evbmips/loongson/dev/glxreg.h
70
#define GCSC_GLIU_STATISTIC_ACTION1 (GCSC_GLIU_MSR_BASE + 0xa6)
sys/arch/evbmips/loongson/dev/glxreg.h
71
#define GCSC_GLIU_STATISTIC_CNT2 (GCSC_GLIU_MSR_BASE + 0xa8)
sys/arch/evbmips/loongson/dev/glxreg.h
72
#define GCSC_GLIU_STATISTIC_MASK2 (GCSC_GLIU_MSR_BASE + 0xa9)
sys/arch/evbmips/loongson/dev/glxreg.h
73
#define GCSC_GLIU_STATISTIC_ACTION2 (GCSC_GLIU_MSR_BASE + 0xaa)
sys/arch/evbmips/loongson/dev/glxreg.h
74
#define GCSC_GLIU_RQ_COMP_VAL (GCSC_GLIU_MSR_BASE + 0xc0)
sys/arch/evbmips/loongson/dev/glxreg.h
75
#define GCSC_GLIU_RQ_COMP_MASK (GCSC_GLIU_MSR_BASE + 0xc1)
sys/arch/evbmips/loongson/dev/glxreg.h
76
#define GCSC_GLIU_DA_COMP_VAL_LO (GCSC_GLIU_MSR_BASE + 0xd0)
sys/arch/evbmips/loongson/dev/glxreg.h
77
#define GCSC_GLIU_DA_COMP_VAL_HI (GCSC_GLIU_MSR_BASE + 0xd1)
sys/arch/evbmips/loongson/dev/glxreg.h
78
#define GCSC_GLIU_DA_COMP_MASK_LO (GCSC_GLIU_MSR_BASE + 0xd2)
sys/arch/evbmips/loongson/dev/glxreg.h
79
#define GCSC_GLIU_DA_COMP_MASK_HI (GCSC_GLIU_MSR_BASE + 0xd3)
sys/arch/evbmips/loongson/dev/glxreg.h
81
#define GCSC_GLIU_IOD_BM0 (GCSC_GLIU_MSR_BASE + 0xe0)
sys/arch/evbmips/loongson/dev/glxreg.h
82
#define GCSC_GLIU_IOD_BM1 (GCSC_GLIU_MSR_BASE + 0xe1)
sys/arch/evbmips/loongson/dev/glxreg.h
83
#define GCSC_GLIU_IOD_BM2 (GCSC_GLIU_MSR_BASE + 0xe2)
sys/arch/evbmips/loongson/dev/glxreg.h
84
#define GCSC_GLIU_IOD_BM3 (GCSC_GLIU_MSR_BASE + 0xe3)
sys/arch/evbmips/loongson/dev/glxreg.h
85
#define GCSC_GLIU_IOD_BM4 (GCSC_GLIU_MSR_BASE + 0xe4)
sys/arch/evbmips/loongson/dev/glxreg.h
86
#define GCSC_GLIU_IOD_BM5 (GCSC_GLIU_MSR_BASE + 0xe5)
sys/arch/evbmips/loongson/dev/glxreg.h
87
#define GCSC_GLIU_IOD_BM6 (GCSC_GLIU_MSR_BASE + 0xe6)
sys/arch/evbmips/loongson/dev/glxreg.h
88
#define GCSC_GLIU_IOD_BM7 (GCSC_GLIU_MSR_BASE + 0xe7)
sys/arch/evbmips/loongson/dev/glxreg.h
89
#define GCSC_GLIU_IOD_BM8 (GCSC_GLIU_MSR_BASE + 0xe8)
sys/arch/evbmips/loongson/dev/glxreg.h
90
#define GCSC_GLIU_IOD_BM9 (GCSC_GLIU_MSR_BASE + 0xe9)
sys/arch/evbmips/loongson/dev/glxreg.h
91
#define GCSC_GLIU_IOD_SC0 (GCSC_GLIU_MSR_BASE + 0xea)
sys/arch/evbmips/loongson/dev/glxreg.h
92
#define GCSC_GLIU_IOD_SC1 (GCSC_GLIU_MSR_BASE + 0xeb)
sys/arch/evbmips/loongson/dev/glxreg.h
93
#define GCSC_GLIU_IOD_SC2 (GCSC_GLIU_MSR_BASE + 0xec)
sys/arch/evbmips/loongson/dev/glxreg.h
94
#define GCSC_GLIU_IOD_SC3 (GCSC_GLIU_MSR_BASE + 0xed)
sys/arch/evbmips/loongson/dev/glxreg.h
95
#define GCSC_GLIU_IOD_SC4 (GCSC_GLIU_MSR_BASE + 0xee)
sys/arch/evbmips/loongson/dev/glxreg.h
96
#define GCSC_GLIU_IOD_SC5 (GCSC_GLIU_MSR_BASE + 0xef)
sys/arch/evbmips/loongson/dev/glxreg.h
97
#define GCSC_GLIU_IOD_SC6 (GCSC_GLIU_MSR_BASE + 0xf0)
sys/arch/evbmips/loongson/dev/glxreg.h
98
#define GCSC_GLIU_IOD_SC7 (GCSC_GLIU_MSR_BASE + 0xf1)